Dmitry Osipov

Development of the read-out ASIC for muon chambers of the CBM experiment

A front-end ASIC for GEM detectors readout in the CBM experiment is presented. The design has the following features: dynamic range of 100 fC, channel hit rate of 2 MHz, ENC of 1000 e- at 50 pF, power comsumption of 10 mW per channel, 6 bit SAR ADC. The chip includes 8 analog processing chains, each consisting of preamplifier, two shapers (fast and slow), differential comparator and an area efficient 6 bit SAR ADC with 1.2 mW power consunption at 50 Msps. The chip also includes the threshold DAC and the digital part.

A new current stimulator architecture for visual cortex stimulation

In this paper a new switched reference stimulator architecture for the visual cortex stimulation is presented. Compared with the present alternatives the architecture allows to relax twice requirements of the stimulator output voltage tolerance and to simplify the design of high voltage (HV) switches. The stimulator functionality was proven by fabrication with AMS HV 0.35 μm CMOS technology and the measurement of test chip. The measurement results show the possibility to drive currents from -10 mA up to 10 mA into the tissue, while the electrode-tissue interface resistance is up to 8 kΩ with the effectively high-voltage output compliance of up to 180 V. Wherein the need for HV VDD voltage is limited to 90 V.

Two-step monotonic switching scheme for low-power SAR ADCs

In this paper the simple method to reduce the switching energy of capacitive digital-to-analog converters (DACs) in low-power successive approximation register (SAR) analog-to-digital converters (ADCs) is described. The method is based on the well-known monotonic switching procedure and the use of one intermediate voltage level during switching. Unlike most recently published switching methods the proposed method does not require the intermediate voltage to be accurate. The implementation of digital control and an intermediate voltage-level generator is considered. To evaluate the reduction in switching energy compared to the conventional monotonic switching procedure, the behavioral model of a 10-bit ADC was examined. The additional digital logic, voltage generator, and capacitive DAC were modeled at the transistor level using a 65 nm STM design kit. Simulation results and the subsequent power efficiency gains are presented.

A novel HV-switch scheme with gate-source overvoltage protection for bidirectional neural interfaces

In this paper a novel high-voltage switch with gate-source overvoltage protection is presented for use in high voltage bidirectional neural interfaces. The proposed switch can tolerate the voltage difference up to 120V between its terminals. The control circuit guarantees the operation of HV transistors in the Safe Operation Area (SOA) by use of the proposed switched voltage follower. The switch can be controlled with low voltage control signals compatible with standard CMOS logic levels. The simulation of the switch performance was carried out with AMS HV 0.35 μm Design Kit.

Current driver with read-out HV protection for neural stimulation

This paper presents a current driver with a novel high voltage (HV) switch schematic for the use as a protective switch for recording circuits during the stimulation sequence. The current driver can source and sink currents of amplitudes up to ±8.2 mA with HV tolerance from 30 V up to 120 V. The mismatch between the sourced and sinked current does not exceed 20 μA. The inter pulse current is no more than 60 pA. The output HV compliance depends on the HV supply voltage with maximum value of the 120 V. The proposed HV switch also tolerates the voltage difference up to 120V between its terminals. The chip was fabricated with AMS HV 0.35 μm CMOS technology.

Linearity analysis of single-ended SAR ADC with split capacitive DAC

This paper proposes the design of a 6-bit single-ended SAR ADC with a variable sampling rate at a maximum achievable speed of 50 MS/s. The SAR ADC utilizes the split capacitor array DAC with a non-conventional split-capacitor value. The influence of switches in the capacitive DAC on the ADCs non-linearity is analysed. According to the fulfilled analysis the recommendations for switches and capacitor array dimensioning are given to provide a minimum differential non-linearity (DNL). At a sampling rate of 50 MS/s, the SAR ADC achieves an ENOB of 5.4 bit at an input signal frequency of 1 MHz and consumes 1.2 mW at a 1.8 V power supply, resulting in an energy efficiency of 568 fJ/conv.-step. The SAR ADC was simulated with parasitics in a standard 180nm CMOS process.

A 50MS/s low-power 8-bit dynamic voltage comparator in 0.18μm CMOS process

This paper describes a design technique for multi-stage high speed precision low-current consumption comparator utilizing charge-storage pre-amplifier. To reduce the average current consumption of the preamplifier capacitive dynamic load is used. To correct the offset voltage of pre-amplifier the OOS (Output Offset Storage) method is used. Presented technique is verified by design of 50 MS/s comparator in standard 0.18 μm CMOS process. Achieved power consumption of preamplifier is 18 μA, providing the input resolution less than 4 mV.

8 Channel neural stimulation ASIC for epidural visual cortex stimulation with on board 90 ppm/°C current reference

This paper presents an 8 channel neural stimulator ASIC for biphasic stimulation of the visual cortex, realized in a 0.35 μm AMS HV process. Each channel is composed of an SPI interface, an 8-bit current digital-to-analog converter (DAC) and 120 V compliant HV output stage. Thus it is possible to deliver to the tissue arbitrary current waveforms with amplitudes up to ±10.24 mA with 40 μA steps. According to the simulation results the maximum differential non-linearity is equal to 0.27 LSB. The on board current reference provides the output current of 16 μA with the variation of 90 ppm/°C in the temperature range of 0-85° C. While the anodic and cathodic currents mismatch does not exceed 13 μA. The HV output interface of the ASIC was previously fabricated and measured. The measured interpulse leakage current does not exceed 60 pA.

2.2ppm/°C bandgap voltage reference with high-order temperature compensation

A 2.2-ppm/°C voltage reference is proposed for use as an analog to digital conversion reference in readout application-specific integrated circuits. The proposed circuit uses resistors available for the standard CMOS process with opposite sign temperature coefficients. That enables a superposition of two bandgap schemes, one with downward concave and the other upward concave voltage temperature dependence. Using two similar schemes for the task allows topology matching of single circuit elements. The providen schematic is verified by simulation of the reference in 0.35 μm technology. The simulated reference provides a voltage of about 1.2 mV with the variation of ~300 μV in the temperature range -20 to 85°C. The operating temperature range is the reduced industrial grade, with a supply voltage of 3.3V, and an average consumption current of 6:4μA in the operating temperature range.

Simulation-based design procedure for sub 1V CMOS current reference

This paper presents a new compact low supply current reference and a simulation-based design procedure to establish the circuit parameters quickly and efficiently. To verify the proposed design procedure, two sub 1 V example circuits for two different reference current values (80 nA and 800 nA) were designed and simulated using 0.35 μm CMOS technology. The circuits are robust against supply voltage variation without the need for external bandgap. A line sensitivity of approximately 1–2%/V over the supply voltage range from sub 1 V is achieved in both cases. The simulated temperature coefficient (TC) values are 93 ppm/ C and 197 ppm/° C in the temperature range from 0°C to 120° C for the 800 nA and 80 nA references, respectively.