Dohyun Baek

A Study on the Electrical Characteristic Analysis of c-Si Solar Cell Diodes

A study on the electrical characteristic analysis of solar cell diodes under experimental conditions of varying temperature and frequency has been conducted. From the current-voltage (I-V) measurements, at the room temperature, we obtained the ideality factor (n) for Space Charge Region (SCR) and Quasi-Neutral Region (QNR) of 3.02 and 1.76, respectively. Characteristics showed that the value of n (at SCR) decreases with rising temperature and n (at QNR) increases with the same conditions. These are due to not only the sharply increased SCR current flow but the activated carrier recombination in the bulk region caused by defects such as contamination, dangling bonds. In addition, from the I-V measurements implemented to confirm the junction uniformity of cells, the average current dispersion was 40.87% and 10.59% at the region of SCR and QNR, respectively. These phenomena were caused by the pyramidal textured junction structure formed to improve the light absorption on the devices front surface, and these affect to the total diode current flow. These defect and textured junction structure will be causes that solar cell diodes have non-ideal electrical characteristics compared with general p-n junction diodes. Also, through the capacitance-voltage (C-V) measurements under the frequency of 180 kHz, we confirmed that the value of built-in potential is 0.63 V. Index Terms—Solar cell diodes, junction uniformity, non-ideal characteristic, I-V, C-V

Effects of electron trapping and interface state generation on bias stress induced in indium–gallium–zinc oxide thin-film transistors

The electrical characteristics of bias temperature stress (BTS) induced in amorphous indium–gallium–zinc oxide thin-film transistors (a-IGZO TFTs) were studied. We analyzed the threshold voltage (VTH) shift on the basis of the effects of positive bias temperature stress (PBTS) and negative bias temperature stress (NBTS), and applied it to the stretched-exponential model. Both stress temperature and bias are considered as important factors in the electrical instabilities of a-IGZO TFTs, and the stretched-exponential equation is well fitted to the stress condition. VTH for the drain current–gate voltage (IDS–VGS) curve and flat-band voltage (VFB) for the capacitance–voltage (C–V) curve move in the positive direction when PBTS is induced. However, in the case of NBTS, they move slightly in the negative direction. To clarify the VTH shift phenomenon by electron and hole injection, the average effective energy barrier (Eτ) is extracted, and the extracted values of Eτ under PBTS and NBTS are about 1.33 and 2.25 eV, respectively. The oxide trap charges (Not) of PBTS and NBTS calculated by C–V measurement are 4.4 × 1011 and 1.49 × 1011 cm−2, respectively. On the other hand, the border trap charges of PBTS and NBTS are 6.7 × 108 and 1.7 × 109 cm−2, respectively. This indicates that the increased interface trap charge, after PBTS is induced, captures electrons during detrap processing from the border trap to the conduction band, valence band, and interface trap.

Effect of Bias Temperature Stress on the Anti-Reflection HfO2 Layer in Complementary Metal Oxide Semiconductor Image Sensors

The effects of various electrical characteristics of HfO2 in CMOS image sensors on bias-thermal stress instability were evaluated. In this work, the HfO2 dielectric layer was used as the anti-reflection layer of image sensors because it had negative charges and could electrically form a p+ layer on a silicon photodiode surface. After the HfO2 layer was stressed with electric field 0.5 MV/cm, 200 °C, and 10 min, there was severe electrical degradation such as +18.8 V flatband voltage shift. In order to investigate this degradation, the oxide trap charges and border trap charges of the HfO2 layer were measured and calculated. Based on these results, the interface trap density and minority carrier generation lifetime, which are directly related to the dark current in CMOS image sensors, were measured. The interface trap density degraded from 4.5×1011 to 1.0×1012 cm-1 eV-1 and the generation lifetime also degraded from 983 to 17 µs after stress application. This trap generated degradation model is suggested for CMOS image sensors. Therefore, pre-stabilization of bias-thermal stress should be implemented to use the HfO2 layer in modern CMOS image sensors.