Byoungdeog Choi

Analysis of Tide-Gauge Records of the 1883 Krakatau Tsunami

The 1883 Krakatau volcanic eruption has generated giant tsunami waves reached heights of 40 m above sea level. Sea level oscillations related with this event have been reported in the Indian, Atlantic and Pacific Oceans. Main goal of this study is to analyze all available tide-gauge records (35) of this event. They are digitized with time step 2 min and processed. First of all, the tidal components are calculated and eliminated from the records. Filtered tide-gauge records are used to re-determine the observed tsunami characteristics (positive and negative amplitudes, wave heights). The results of given analysis are compared with the results of the direct numerical simulation of the tsunami wave propagation in the framework of the linear shallow-water theory using the ETOPO2 bathymetry.

A Study on the Electrical Characteristic Analysis of c-Si Solar Cell Diodes

A study on the electrical characteristic analysis of solar cell diodes under experimental conditions of varying temperature and frequency has been conducted. From the current-voltage (I-V) measurements, at the room temperature, we obtained the ideality factor (n) for Space Charge Region (SCR) and Quasi-Neutral Region (QNR) of 3.02 and 1.76, respectively. Characteristics showed that the value of n (at SCR) decreases with rising temperature and n (at QNR) increases with the same conditions. These are due to not only the sharply increased SCR current flow but the activated carrier recombination in the bulk region caused by defects such as contamination, dangling bonds. In addition, from the I-V measurements implemented to confirm the junction uniformity of cells, the average current dispersion was 40.87% and 10.59% at the region of SCR and QNR, respectively. These phenomena were caused by the pyramidal textured junction structure formed to improve the light absorption on the devices front surface, and these affect to the total diode current flow. These defect and textured junction structure will be causes that solar cell diodes have non-ideal electrical characteristics compared with general p-n junction diodes. Also, through the capacitance-voltage (C-V) measurements under the frequency of 180 kHz, we confirmed that the value of built-in potential is 0.63 V. Index Terms—Solar cell diodes, junction uniformity, non-ideal characteristic, I-V, C-V

SiO2 Films Deposited by APCVD with a TEOS/Ozone Mixture and Its Application to the Gate Dielectric of TFTs

Silicon dioxide (SiO 2 ) films were deposited using atmospheric pressure chemical vapor deposition (APCVD) with tetraethyl orthosilicate (TEOS) and ozone (O 3 ) as reactant gases. These films were used as the gate dielectric of low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs). 0 3 gas was chosen instead of oxygen (0 2 ) gas because the latter is not compatible with the low temperature processing of LTPS TFTs. SiO 2 films deposited at low temperatures (<450°C) have low Si-OH contents and electrical properties desirable for gate insulator materials. Although the LTPS TFTs were fabricated using low cost SiO 2 films deposited by APCVD as the gate dielectric, the fabricated devices exhibited a field-effect mobility of 49 cm 2 /V s and a subthreshold swing of 490 mV/dec. The results demonstrate that SiO 2 deposited by APCVD with TEOS and 0 3 is a promising material for low cost and high quality gate insulators for LTPS TFTs.

Band gap and defect states of MgO thin films investigated using reflection electron energy loss spectroscopy

The band gap and defect states of MgO thin films were investigated by using reflection electron energy loss spectroscopy (REELS) and high-energy resolution REELS (HR-REELS). HR-REELS with a primary electron energy of 0.3 keV revealed that the surface F center (FS) energy was located at approximately 4.2 eV above the valence band maximum (VBM) and the surface band gap width (EgS) was approximately 6.3 eV. The bulk F center (FB) energy was located approximately 4.9 eV above the VBM and the bulk band gap width was about 7.8 eV, when measured by REELS with 3 keV primary electrons. From a first-principles calculation, we confirmed that the 4.2 eV and 4.9 eV peaks were FS and FB, induced by oxygen vacancies. We also experimentally demonstrated that the HR-REELS peak height increases with increasing number of oxygen vacancies. Finally, we calculated the secondary electron emission yields (γ) for various noble gases. He and Ne were not influenced by the defect states owing to their higher ionization energies, but...

Embedded LTPS flash cells with oxide–nitride–oxynitride stack structure for realization of multi-function mobile flat panel displays

In this paper, embedded flash (eFlash) cells were fabricated for realization of multi-functions, such as systems on panels (SOPs) and threshold voltage (VTH) stabilization of flat panel displays (FPDs). Fabrication was via low temperature polycrystalline silicon (LTPS) thin film transistor (TFT) technology and an oxide–nitride–oxynitride (ONOn) stack structure on glass. Poly-silicon (poly-Si) on glass, which was annealed via an excimer laser, has a very rough surface. To fabricate LTPS eFlash cells on glass with a very rough poly-Si surface, plasma-assisted oxynitridation was performed; nitrous oxide (N2O) served as a reactive gas. LTPS eFlash cells have excellent TFT electrical properties, such as VTH, a high On/Off current ratio and a low sub-threshold swing (S). The results demonstrate that eFlash cells fabricated on glass with a rough silicon surface, via an ONOn stack structure, have switching characteristics suitable for data storage, such as a low operating voltage (<±10 V) suitable for mobile FPDs, a threshold voltage window, ΔVTH, which exceeds 2.3 V, between the programming and erasing (P/E) states, over a period of 10 years, and the capacity to retain the initial ΔVTH over a period of 105 P/E operations.

Band alignment of atomic layer deposited (HfZrO{sub 4}){sub 1−x}(SiO{sub 2}){sub x} gate dielectrics on Si (100)

The band alignment of atomic layer deposited (HfZrO{sub 4}){sub 1−x}(SiO{sub 2}){sub x} (x = 0, 0.10, 0.15, and 0.20) gate dielectric thin films grown on Si (100) was obtained by using X-ray photoelectron spectroscopy and reflection electron energy loss spectroscopy. The band gap, valence band offset, and conduction band offset values for HfZrO{sub 4} silicate increased from 5.4 eV to 5.8 eV, from 2.5 eV to 2.75 eV, and from 1.78 eV to 1.93 eV, respectively, as the mole fraction (x) of SiO{sub 2} increased from 0.1 to 0.2. This increase in the conduction band and valence band offsets, as a function of increasing SiO{sub 2} mole fraction, decreased the gate leakage current density. As a result, HfZrO{sub 4} silicate thin films were found to be better for advanced gate stack applications because they had adequate band gaps to ensure sufficient conduction band offsets and valence band offsets to Si.

Cost-Effective Silicon Vertical Diode Switch for Next-Generation Memory Devices

In this letter, a cost-effective vertical diode scheme for next-generation memory devices, including phase-change memories (PCMs), is realized. After the contact formation for diodes with only one mask layer, an amorphous silicon (a-Si) film was deposited within the contacts using SiH4 ramp-up ambient in a conventional batch-type furnace in order to minimize the growth of native oxide. A deposition/etch-back/deposition scheme enabled us to achieve robust vertical diodes without any seams or interfacial oxide layer within the vertical diode pillars. Subsequent annealing at 600 °C provided solid-phase epitaxial alignment of the a-Si layer. An ideality factor revealed that the new scheme provided noticeable crystallinity of the silicon diodes. Moreover, the electrical characteristics of the diodes verified that the scheme was suitable for full operation of PCM devices.

High performance nonvolatile memory using SiO2/SiOx/SiOxNy stack on excimer laser-annealed polysilicon and the effect of blocking thickness on operation voltage

Silicon-rich SiOx material is a good charge storage candidate for memory applications that promise a large memory window and low operation voltage. Nonvolatile memory (NVM) devices fabricated on excimer laser-annealed polysilicon using SiO2/SiOx/SiOxNy (OOxOn) structure are investigated with SiO2 blocking thicknesses changing from 15 to 20 to 30 nm. The Si-rich SiOx material exposed numerous non-bridging oxygen hole-centre defect sources and a rich silicon phase in the base material. These defects, as well as amorphous silicon clusters existing in the SiOx layer, enhance the charge storage capacity of the device. Retention properties were ensured by 3.2 nm SiOxNy tunnelling layer growth via N2O plasma-assisted oxynitridation. NVM characteristics showed a retention exceeding 85% of the threshold voltage shift after 104 s and greater than 70% after 10 years. Depending on the blocking thickness of 15, 20 or 30 nm, operating voltages varied from ±9 to ±13 V at a programming/erasing duration of only 1 ms. These excellent operating properties of the OOxOn structure make it a potential competitor among the new generation of memory structures on glass.

Selective Epitaxial Growth of Silicon for Vertical Diode Application

Selectivity control in silicon selective epitaxial growth (SEG) for deep contact patterns, which is one of the key processes for silicon-based stacked devices and cell switches for next generation memories, was studied. Absolute values of selectivity loss during silicon SEG using the most popular H2/dichlorosilane (DCS)/HCl gas system were evaluated using a commercialized inspection tool in 200 mm wafers with real contact patterns. It was revealed that HCl/(DCS+HCl) ratio and the contact structure played a crucial role in suppressing selectivity loss. The number of selectivity losses in an entire wafer was less than 100 when the HCl/(DCS+HCl) ratio was larger than 0.41. The vertical pn diode prepared using the silicon SEG process with elaborate selectivity control showed more remarkable electrical abilities to accommodate current flow than polycrystalline silicon (poly-Si), including the ideality factor and swing, and reverse leakage current.

Stability enhancement of polysilicon thin-film transistors using stacked plasma-enhanced chemical vapor deposited SiO2/SiNx gate dielectric

The use of a double-layer, plasma-enhanced chemical vapor deposited SiO2/SiNx film as a gate dielectric material for polysilicon thin-film transistors was investigated in order to reduce mobile ion contamination and to improve gate oxide integrity degradation. We observed that the interposed silicon nitride film between the gate electrode and the SiO2 gate insulator prevents the incorporation of mobile ions into the SiO2 film, and also increases the breakdown voltage of the gate-insulating film. The mobile ion densities for the double SiO2/SiNx and single SiO2 gate dielectrics (no interposed SiNx layer between the gate electrode and SiO2 gate insulator) were 1.3 ×1011 and 1.7 ×1012/cm2, respectively. The breakdown fields at the 50% failure points in the Weibull plots for the double and single dielectric cases were 8 and 5 MV/cm, respectively. We conclude that the silicon nitride layer of the double gate insulator film minimizes ion contamination, leading to the enhancement of breakdown characteristics.