Pyungho Choi

A Study on the Electrical Characteristic Analysis of c-Si Solar Cell Diodes

A study on the electrical characteristic analysis of solar cell diodes under experimental conditions of varying temperature and frequency has been conducted. From the current-voltage (I-V) measurements, at the room temperature, we obtained the ideality factor (n) for Space Charge Region (SCR) and Quasi-Neutral Region (QNR) of 3.02 and 1.76, respectively. Characteristics showed that the value of n (at SCR) decreases with rising temperature and n (at QNR) increases with the same conditions. These are due to not only the sharply increased SCR current flow but the activated carrier recombination in the bulk region caused by defects such as contamination, dangling bonds. In addition, from the I-V measurements implemented to confirm the junction uniformity of cells, the average current dispersion was 40.87% and 10.59% at the region of SCR and QNR, respectively. These phenomena were caused by the pyramidal textured junction structure formed to improve the light absorption on the devices front surface, and these affect to the total diode current flow. These defect and textured junction structure will be causes that solar cell diodes have non-ideal electrical characteristics compared with general p-n junction diodes. Also, through the capacitance-voltage (C-V) measurements under the frequency of 180 kHz, we confirmed that the value of built-in potential is 0.63 V. Index Terms—Solar cell diodes, junction uniformity, non-ideal characteristic, I-V, C-V

Band gap and defect states of MgO thin films investigated using reflection electron energy loss spectroscopy

The band gap and defect states of MgO thin films were investigated by using reflection electron energy loss spectroscopy (REELS) and high-energy resolution REELS (HR-REELS). HR-REELS with a primary electron energy of 0.3 keV revealed that the surface F center (FS) energy was located at approximately 4.2 eV above the valence band maximum (VBM) and the surface band gap width (EgS) was approximately 6.3 eV. The bulk F center (FB) energy was located approximately 4.9 eV above the VBM and the bulk band gap width was about 7.8 eV, when measured by REELS with 3 keV primary electrons. From a first-principles calculation, we confirmed that the 4.2 eV and 4.9 eV peaks were FS and FB, induced by oxygen vacancies. We also experimentally demonstrated that the HR-REELS peak height increases with increasing number of oxygen vacancies. Finally, we calculated the secondary electron emission yields (γ) for various noble gases. He and Ne were not influenced by the defect states owing to their higher ionization energies, but...

Band alignment of atomic layer deposited (HfZrO{sub 4}){sub 1−x}(SiO{sub 2}){sub x} gate dielectrics on Si (100)

The band alignment of atomic layer deposited (HfZrO{sub 4}){sub 1−x}(SiO{sub 2}){sub x} (x = 0, 0.10, 0.15, and 0.20) gate dielectric thin films grown on Si (100) was obtained by using X-ray photoelectron spectroscopy and reflection electron energy loss spectroscopy. The band gap, valence band offset, and conduction band offset values for HfZrO{sub 4} silicate increased from 5.4 eV to 5.8 eV, from 2.5 eV to 2.75 eV, and from 1.78 eV to 1.93 eV, respectively, as the mole fraction (x) of SiO{sub 2} increased from 0.1 to 0.2. This increase in the conduction band and valence band offsets, as a function of increasing SiO{sub 2} mole fraction, decreased the gate leakage current density. As a result, HfZrO{sub 4} silicate thin films were found to be better for advanced gate stack applications because they had adequate band gaps to ensure sufficient conduction band offsets and valence band offsets to Si.

Defect visualization of Cu(InGa)(SeS)2 thin films using DLTS measurement

Defect depth profiles of Cu (In1−x,Gax)(Se1−ySy)2 (CIGSS) were measured as functions of pulse width and voltage via deep-level transient spectroscopy (DLTS). Four defects were observed, i.e., electron traps of ~0.2 eV at 140 K (E1 trap) and 0.47 eV at 300 K (E2 trap) and hole traps of ~0.1 eV at 100 K (H1 trap) and ~0.4 eV at 250 K (H2 trap). The open circuit voltage (VOC) deteriorated when the trap densities of E2 were increased. The energy band diagrams of CIGSS were also obtained using Auger electron spectroscopy (AES), X-ray photoelectron spectroscopy (XPS), and DLTS data. These results showed that the valence band was lowered at higher S content. In addition, it was found that the E2 defect influenced the VOC and could be interpreted as an extended defect. Defect depth profile images provided clear insight into the identification of defect state and density as a function of depth around the space charge region.

Direct band gap measurement of Cu(In,Ga)(Se,S)2 thin films using high-resolution reflection electron energy loss spectroscopy

To investigate the band gap profile of Cu(In1−x,Gax)(Se1−ySy)2 of various compositions, we measured the band gap profile directly as a function of in-depth using high-resolution reflection energy loss spectroscopy (HR-REELS), which was compared with the band gap profile calculated based on the auger depth profile. The band gap profile is a double-graded band gap as a function of in-depth. The calculated band gap obtained from the auger depth profile seems to be larger than that by HR-REELS. Calculated band gaps are to measure the average band gap of the spatially different varying compositions with respect to considering its void fraction. But, the results obtained using HR-REELS are to be affected by the low band gap (i.e., out of void) rather than large one (i.e., near void). Our findings suggest an analytical method to directly determine the band gap profile as function of in-depth.

Hot hole-induced device degradation by drain junction reverse current

Abstract In this paper, device degradation mechanisms by drain junction reverse current in the off-state were studied, using n-type metal–oxide–semiconductor field-effect transistor (N-MOSFET), which is used as the high-voltage core circuit of flash memory chip. Components of drain leakage currents in the off-state are gate-induced drain-leakage (GIDL) and drain junction reverse currents. Device degradation phenomenon and mechanism by GIDL in the MOSFETs have been well known, but those by drain junction reverse current have not. A variety of measurement conditions for separating drain junction reverse current from total drain current in the off-state were suggested, and hole injection phenomenon into the gate was investigated through the modified capacitive-voltage method. In addition, we investigated the location of electron–hole generation between GIDL and drain junction reverse current through the lateral profile of trapped hole extracted from charge pumping method.

A Study on the Fluorine Effect of Direct Contact Process in High-Doped Boron Phosphorus Silicate Glass (BPSG)

The effect of fluorine ions, which can be reacted with boron in high-doped BPSG, is investigated on the contact sidewall wiggling profile in semiconductor process. In the semiconductor device, there are many contacts on p+/n+ source and drain region. However these types of wiggling profile is only observed at the n+ contact region. As a result, we find that the type of plug implantation dopant can affect the sidewall wiggling profile of contact. By optimizing the proper fluorine gas flow rate, both the straight sidewall profile and the desired electrical characteristics can be obtained. In this paper, we propose a fundamental approach to improve the contact sidewall wiggling profile phenomena, which mostly appear in high-doped BPSG on nextgeneration DRAM products.

Effect of Bias Temperature Stress on the Anti-Reflection HfO2 Layer in Complementary Metal Oxide Semiconductor Image Sensors

The effects of various electrical characteristics of HfO2 in CMOS image sensors on bias-thermal stress instability were evaluated. In this work, the HfO2 dielectric layer was used as the anti-reflection layer of image sensors because it had negative charges and could electrically form a p+ layer on a silicon photodiode surface. After the HfO2 layer was stressed with electric field 0.5 MV/cm, 200 °C, and 10 min, there was severe electrical degradation such as +18.8 V flatband voltage shift. In order to investigate this degradation, the oxide trap charges and border trap charges of the HfO2 layer were measured and calculated. Based on these results, the interface trap density and minority carrier generation lifetime, which are directly related to the dark current in CMOS image sensors, were measured. The interface trap density degraded from 4.5×1011 to 1.0×1012 cm-1 eV-1 and the generation lifetime also degraded from 983 to 17 µs after stress application. This trap generated degradation model is suggested for CMOS image sensors. Therefore, pre-stabilization of bias-thermal stress should be implemented to use the HfO2 layer in modern CMOS image sensors.

Reliability Improvement in Solution-Processed ZrO2 Dielectrics Due to Addition of H2O2

In this study, we investigated the effects of hydrogen peroxide (H2O2) on solution-processed zirconium oxide (ZrO2) dielectric materials. The addition of H2O2 into ZrO2 dielectric showed a reduction in hysteresis capacitance-voltage characteristics (from 393 mV to 96 mV). This resulted in a reduction in border trap density (Nbt) of the ZrO2 film (ZrO2: 2.24 × 1011 cm-2, ZrO2 + H2O2: 3.96 × 1010 cm-2). In addition, use of H2O2 in the ZrO2 dielectric improved the interface quality. Specifically, the reduced number of trap sites improved the reliability of the device under a negative bias stress (NBS). The 350 °C annealed ZrO2 dielectric with H2O2 showed excellent leakage current properties (6.7 × 10-9 A/cm2 at gate voltage of -10 V). Based on these results, we fabricated IGZO/ZrO2 + H2O2 TFTs, which showed a high saturation mobility of 6.10 cm2/V · s and excellent switching properties. This study suggests that incorporation of H2O2 into ZrO2 effectively reduced oxygen vacancies through strong oxidation and minimized residual organics that cause impurities or structural defects, such as pores or pin holes, compared to a virgin ZrO2 film.

Electrical Characterization of Charge Polarity in AlF3 Anti-Reflection Layers for Complementary Metal Oxide Semiconductor Image Sensors

In this study, the charge polarity of aluminum fluoride (AlF3) as a function of varying thickness (tAlF3 = 20, 35, 50, 65, and 80 nm) was discussed. AlF3 films were deposited onto p-Si wafers via electron beam sputtering. Thickness dependent charge polarity and reliability issues under bias-temperature stress conditions were identified using a capacitance-voltage (C-V) characterization method. AlF3 was found to possess negative fixed charges, leading to a C-V curve shift toward the positive gate bias direction as tAlF3 was increased up to 50 nm. On the contrary, the C-V characteristics were dominantly affected by the positive charges of mobile ions and/or fluorine vacancies when tAlF3 was increased to more than 50 nm. Additionally, negative bias temperature stress (1 MV/cm, 473 K for 10 mins) increased insulator trapped charges and decreased interface traps in 20 nm thick AlF3 films. These results could be attributed to positively charged fluorine vacancies introduced by broken Al-F bonds within AlF3 films and the passivation of Si dangling bonds due to broken fluorine ions at the interface, respectively. It was believed that 20 nm thick AlF3 films sufficiently attracted holes from the Si substrate, forming a hole accumulation layer on the surface due to total charge polarity of the AlF3 dielectric being entirely governed by negative fixed charges as the thickness of AlF3 decreased. Based on these results, AlF3 films are proposed for use as an anti-reflection layer to replace HfO2 in CMOS image sensors.