Don Bouldin

Enhancing reliability and flexibility of a system-on-chip using reconfigurable logic

In this paper we present the design of a SoC baseline platform with a Leon2 CPU. An Advanced Encryption Standard (AES) module and a reconfigurable core form the IP blocks that are attached to the SoC through AMIBA bus. The reconfigurable core is inserted into the design using tools developed by DAFCA, Inc. (Design Automation for Flexible Chip Architectures) for post-silicon debugging and verification. Hence, a re-spin may be avoided and the time-to-market will be reduced.

Enhancing electronic systems with reconfigurable hardware

This article describes how current applications - communications and mobile systems - have employed FPGAs because they are more flexible than ASICs yet with higher speed and lower power consumption than CPUs. This has happened in spite of the fact that we require HDL experts to program them. New applications that can benefit from variable-grain parallelism are hot prospects to emerge as killer applications in the near future, especially as improvements in data movement are made. Enabling these new killer applications can only be accomplished by increasing designer productivity. Graphical tools that provide reusable components and means of expressing parallelism hold great promise in achieving these goals

Enhancement of MCM testability using an embedded reconfigurable FPGA

The testability of an MCM can be enhanced significantly for very little cost whenever a reprogrammable FPGA component that is already embedded in the MCM for functionality is utilized for diagnostics. This approach can have some of the characteristics of a smart substrate which uses the scan cell beside-the-signal-path (BSP) methodology. The design and implementation of an MCM with this capability is presented along with descriptions of the self-test algorithms, fault isolation and real-time testing and monitoring that this method provides.

Performance comparison of MCM-D and SMT packaging technologies for a DSP subsystem

Advanced packaging technologies such as MCMs offer superior performance as compared to the conventional PCB technologies. This paper discusses the design, development, and comparison of a general purpose programmable DSP subsystem packaged in MCM and conventional surface-mount technologies. The subsystem contains a 32-bit floating-point programmable DSP processor along with 256 K-bytes of SRAM, 128 K-bytes of flash memory, a 10 K-gate FPGA, and a 6-channel 12-bit ADC. The complete subsystem has been interconnected on a 37 mm by 37 mm MCM-D substrate and is packaged in a 320-pin ceramic quad flatpack. This paper evaluates electrical and thermal performance for the MCM-D substrate and compares the results with the SMT version of the design.

Multi-FPGA partitioning method based on topological levelization

This paper presents a partitioning method based on topological ordering and levelization. The proposed method, termed RPL, performs multi-FPGA partitioning by taking into account six different partitioning constraints. We also compare RPL to two existing algorithms. The first approach is a hierarchical partitioning method based on topological ordering (HP). The second approach is a recursive algorithm based on the Fiduccia and Mattheyses bipartitioning heuristic (RP). Experimental results on seven application benchmarks mapped onto three different hardware architectures demonstrated that the proposed RPL approach achieved fewer partitions in less time when compared to the RP and HP algorithms.

Experiences Teaching Physical Synthesis of FPGAs and ASICs

Interconnect delays dominate gate delays in integrated circuits fabricated using 180-nm feature sizes or below. Hence, no longer can designers separate the logic synthesis function from physical placement and routing but instead must perform physical synthesis to achieve timing closure with a minimum of design cycle iterations. Experiences teaching students to design competitive FPGAs and ASICs using physical synthesis are described in this paper.

Microelectronic Systems Education in the Global Economy Era

Currently, fewer ASIC designers are needed as before and the creation of intellectual property (IP) blocks is being performed in developing countries like India. As a result of this shift in design practices, a microelectronic design methodology that: (1) de-emphasize our traditional ASIC design and fab courses, and (2) concentrates on system integration of IP blocks for programmable SoCs such as XILINX VirtexII-Pro becomes an attractive alternative to more traditional ASIC style experiences. Both the University of New Hampshire and the University of Tennessee are restructuring our own curricula to respond to these challenges. We do not plan to eliminate entirely our custom VLSI courses which deal with physical level issues such as signal integrity, design for testability and design for manufacturability. However, we recognize that the number of ASIC design starts is continuing to go down while the number of FPGA designs is increasing. At the same time, we realize that globalization of engineering design means that many of the IP blocks needed for applications will be designed overseas, not in the USA. On the bright side, we believe that US designers will still be needed but will focus more on customizing FPGA platforms to the needs of local customers. Thus, we need to emphasize our FPGA-based courses even more than in the past and concentrate on providing students with team projects that sharpen their skills in developing specifications, integrating IP blocks and filling in new ones where needed, and in verification using both simulation and FPGA-based prototype boards. Because of collaboration, learning management tools, non-technical and technical components become equally important. Both centralized and global educational models are presented and collaboration scenarios proposed for consideration and discussion.

Synthesis of FPGAs and Testable ASICs

Industrial designers and educators who plan to design microelectronic systems (e.g. hardware accelerators, co-processors, etc.) are increasingly capturing their designs using hardware description languages such as VHDL and Verilog. The designs are then most often synthesized into programmable logic components such as field-programmable gate arrays (FPGAs) offered by Xilinx, Altera, Actel and others. This approach places the emphasis on high-level design which reduces time to market by relying on synthesis software and programmable logic to produce working prototypes rapidly. These prototypes may then be altered as requirements change or converted into high-volume mask gate arrays or other application-specific integrated circuits (ASICs) when the demand is known to be sufficient. These ASICs, however, must be designed to be testable to screen out those with manufacturing defects. Hence, scan logic must be inserted, test vectors generated and fault grading performed to ensure a high level of testability. These efforts complicate and delay the conversion of FPGA designs to ASICs but must be considered by designers of microelectronic systems. Topics covered include: design flow; system partitioning; hardware description languages (HDLs); specifying behavioral control; specifying structural components; critical paths; placement and routing; technology choices; FPGA applications; rapid prototyping; retargeting; manufacturing defects; scan chain insertion; test vector generation; fault grading, and ASIC production

Cryptographic key protection module in hardware for the Need2Know system

Traditional public key cryptographic methods provide access control to sensitive data by allowing the message sender to grant a single recipient permission to read the encrypted message. The Need2Knowreg system (N2K) improves upon these methods by providing role-based access control. N2K defines data access permissions similar to those of a multiuser file system, but N2K strictly enforces access through cryptographic standards. Since custom hardware can efficiently implement many cryptographic algorithms and can provide additional security, N2K stands to benefit greatly from a hardware implementation. To this end, the main N2K algorithm, the Key Protection Module (KPM), is being specified in VHDL. The design is being built and tested incrementally: this first phase implements the core control logic of the KPM without integrating its cryptographic sub-modules. Both RTL simulation and formal verification are used to test the design. This is the first N2K implementation in hardware, and it promises to provide an accelerated and secured alternative to the software-based system. A hardware implementation is a necessary step toward highly secure and flexible deployments of the N2K system

ASIC by design: automated design of digital signal processing application-specific integrated circuits

Comparing the optimized results to the baseline, we are achieving typically 10-20/spl times/ improvement in PDA. This allows gap closure to approach the optimization of a full custom design process while preserving the automation and design efficiency of ASIC design. Additionally, the reuse of each macro saves two to three staff-months, and each optimization script saves one to two staff-months. Hence, we achieve an overall reduction in design time even though it takes extra time to run these optimization tools. The mission-specific processing (MSP) design flow can be applied to a wide range of DSP and other digital processing applications, where high performance and integration is required. The macros developed were selected to span important algorithms commonly performed in communication, radar, navigation, targeting, electronic warfare and other military and national security applications.