Don E. Ross

Heuristics to compute variable orderings for efficient manipulation of ordered binary decision diagrams

Variable ordering is critical in the efficient representation of functions as Ordered Binary Decision Diagrams (OBDDS). In this paper we present new heuristics to determine “good” variable orderings. We use a new representation form, Ordered Partial Decision Diagrams (OPDDs)~ to evaluate heuristically generated orders on large crccuits. Several improved orders are located for benchmark circuits, and an overall ordering strategy is introduced which includes partial functional calculations and which requires insignificant computation resources.

Functional approaches to generating orderings for efficient symbolic representations

The authors present a functional approach to generating orderings for representing functions. They develop a cost function which closely mimics the ordered binary decision diagram operations and can be quickly computed. Using the cost as a metric for an ordering, an annealing procedure was used to arrive at good variable orderings. The results obtained by simulated annealing are compared to orderings generated from heuristics that use circuit topology to arrive at a variable ordering.<<ETX>>

CATAPULT: concurrent automatic testing allowing parallelization and using limited topology

An improved algorithm is presented for identifying redundant faults and finding tests for hard faults in combination circuits. A concurrent approach is proposed which is based on the concepts of functional decomposition, explicit representation of fanout stems, and the Boolean difference. The data structure used is the binary decision diagram. The algorithm operates as a back end to test generators which use random patterns or heuristics or a combination of the two.<<ETX>>

LFSR based deterministic hardware for at-speed BIST

A deterministic test pattern generator for BIST, based on linear feedback shift registers is discussed. A method of designing the test pattern generator in order that it generates deterministic as well as pseudo random patterns is presented. One application of this method is illustrated where deterministic at-speed testing of C-testable ILAs, covering all possible single and multiple combinational faults is achieved. Response analysers are discussed including one with zero aliasing probability. The algorithms for synthesizing the small amount of BIST hardware are explained.<<ETX>>

Signal probability calculations using partial functional manipulation

Signal probability calculations are necessary to determine the random pattern testability of logic circuits. Determination of random pattern testability is necessary for considering the use of weighted or unweighted linear feedback shift registers (LFSRs) as an appropriate testing method. This paper presents an algorithm to accurately and efficiently (both in space and time) calculate signal probabilities (sometimes called syndrome analysis) within digital logic networks. It has the advantage that it uses a new method for signal probability calculations which is typically both fast and accurate, and which has already efficiently produced results for all the ISCAS combinational circuits.<<ETX>>

Exact ordered binary decision diagram size when representing classes of symmetric functions

An ordered binary decision diagram (OBDD) is a canonical, graphical representation of a switching function. The space complexity of this representation as well as the time complexity for manipulating functions in this form is determained by the number of vertices in the OBDD. Symmetric functions are a class of functions which include the basic Boolean gates such as NOT, AND, NAND, NOR, XOR, etc., as well as less basic functions, such as voter logic for redundant circuit implementations. Symmetric functions exploit the most powerful properties of OBDDs to a very great extent. OBDDs have been shown to have size of O(n2), where n is the number of switching variables. However, this says little of the actual performance of OBDDs in practice. Exact equations of OBDD size are derived for the common classes of symmetric functions, as well as an exact equation for the largest OBDD that can exist for any arbitrary symmetric function. It is shown that OBDDs are Ω(n2) for the majority of functions from each common class of symmetric functions beyond the simplest Boolean gates. Since most functions can be expected to be more complex to represent than symmetric functions, this result has profound implications to the straightforward application of OBDDs to large functional problems.

Linear finite state machine for lD ILAs

Linear Finite State Machine for One Dimensional (1D) Iterative Logic Arrays (ILAs) is described. The technique for modifying the Linear Feedback Shift Register (LFSR) based test generator called Linear Finite State Machine (LFSM) for deterministic test pattern generation is discussed and extended for generating the test vectors for 1D unilateral ILAs. One Repetition Length (ORL) of C-testable ILAs and unique characteristics of the C-testable test patterns are used for the compact design of the LFSM based at-speed Built-in Self Test (BIST). Such LFSM based BIST occupies small silicon area, simplifies the design of the controller and does at-speed testing of the ILAs. This results in reduced time and cost of testing. In addition, the exact probability distribution equations are developed for additional bits needed to map a Finite State Machine (FSM) into an LFSM. The distribution clearly shows that the expected number of additional bits is very small, often zero. The probability distribution equations are equally valid for any LFSR based test generator for other circuits.<<ETX>>

An accurate delay model for BiCMOS gates and off-chip drivers

A delay model for BiCMOS inverters and drivers is reported. This model combines two important features. First, it is valid for a wide range of load capacitances, i.e., from sub-picofarads to tens of picofarads. The model accounts for most of the important device phenomena especially the dependence of the current gain and the forward transit time of the bipolar junction transistors (BJTs) on the collector current level. The second feature is that the model yields accurate closed form expressions for the 50% fall and rise times. The error between the analytical model and simulation program with IC emphasis (SPICE) is for most cases within 10%. The proposed closed form delay expression can be used reliably for device and circuit design applications.<<ETX>>

Built-in self test for C-testable ILA's

Testing of one-dimensional (1-D) unilateral iterative logic arrays (ILAs) of combinational cells with constant test vectors is studied and the concept of one repetition length (ORL) within the tests used for testing C-testable arrays is described. The impact of ORL on the test set size and the design of the test generator are discussed. ORL can dramatically reduce the on-chip test generator size with a negligible increase in the test set size. ORL, coupled with a single distinguishing sequence (DS) for ILAs with cell vertical outputs has proved to be attractive in terms of both reduced test set size and reduced test generator size. ORL testability can be used for C-testable arrays with single faulty cell and multiple faulty cells. The technique for using a single linear finite state machine (LFSM) for generating the necessary deterministic test patterns followed optionally by pseudorandom patterns from the same automaton is discussed. Use of an LFSM as a built-in test generator for only deterministic tests for 1-D ILAs is covered. With ORL, a compact LFSM based built-in self test (BIST) generator can deliver the test vectors to all the cells in the array. The exact probability distribution equation has been developed for additional bits needed to map a nonlinear machine (FSM) definition into a LFSM definition. The distribution clearly shows that the expected number of additional bits is very small, often zero. >

The roles of controllability and observability in design for test

The nature of many problems related to testability requires detailed information about their underlying test parameters. These parameters are commonly referred to as controllability and observability. This research concerns exact measures of detectability, controllability, and observability to measure the relative importance of the latter two on the likelihood of the former. New functional methods for fault analysis are utilized which allow computations not previously possible; the empirical results presented here are an example of such an application.<<ETX>>