M. Ray Mercer

CATAPULT: concurrent automatic testing allowing parallelization and using limited topology

An improved algorithm is presented for identifying redundant faults and finding tests for hard faults in combination circuits. A concurrent approach is proposed which is based on the concepts of functional decomposition, explicit representation of fanout stems, and the Boolean difference. The data structure used is the binary decision diagram. The algorithm operates as a back end to test generators which use random patterns or heuristics or a combination of the two.<<ETX>>

Exact ordered binary decision diagram size when representing classes of symmetric functions

An ordered binary decision diagram (OBDD) is a canonical, graphical representation of a switching function. The space complexity of this representation as well as the time complexity for manipulating functions in this form is determained by the number of vertices in the OBDD. Symmetric functions are a class of functions which include the basic Boolean gates such as NOT, AND, NAND, NOR, XOR, etc., as well as less basic functions, such as voter logic for redundant circuit implementations. Symmetric functions exploit the most powerful properties of OBDDs to a very great extent. OBDDs have been shown to have size of O(n2), where n is the number of switching variables. However, this says little of the actual performance of OBDDs in practice. Exact equations of OBDD size are derived for the common classes of symmetric functions, as well as an exact equation for the largest OBDD that can exist for any arbitrary symmetric function. It is shown that OBDDs are Ω(n2) for the majority of functions from each common class of symmetric functions beyond the simplest Boolean gates. Since most functions can be expected to be more complex to represent than symmetric functions, this result has profound implications to the straightforward application of OBDDs to large functional problems.

ETA: electrical-level timing analysis

A timing analyzer which performs timing analysis considering electrical-level details such as input signal slope, gate input distinction, charge sharing, and interconnect, while also taking into account such high-level concerns as path sensitization, is described. To achieve the greatest efficiency, ETA operates in two phases: (1) logic and delay precharacterization, and (2) longest path analysis. During the precharacterization phase, each gate is analyzed to get its Boolean function and its load at the transistor level. During the longest path analysis phase, paths from each primary input are enumerated and examined separately. Each potentially longest path is tested for sensitizability at the gate level until a sensitizable longest path is found. The circuit examples given demonstrate the importance of an accurate delay calculation in correctly finding the longest statistically sensitizable path.<<ETX>>

Test Performance Evaluation

In order to better understand and continually improve the manufacturing test process, it would be helpful to have a definitive measure of the “quality” of the test sets used. One method of measuring test quality might be to simply monitor the field reject rate - the number of parts returned or reported to the manufacturer as faulty. However, this is a crude measure for several reasons. Circuits can be damaged by a number of post-manufacture phenomena such as electrostatic discharge effects, poor encapsulation or wire bonding, etc. Also, on very complex circuits, some faults may never be detected if the corresponding portion of circuitry is not used by the consumer.

The Contributions of Controllability and Observability to Test

Structural testing is based on the notions of controllability and observability. Controllability generally refers to the application of circuit stimulus such that the presence of a fault will cause some site(s) in the circuit to be logically different than when the fault is absent. Observability concerns the causation of a condition whereby the difference at the site(s) would force a logical difference at some circuit output where it can be directly measured. These quantities will be more formally defined in a later section.

Fault Model Behavior

One aspect of paramount importance in deterministic testing is the performance of the fault models underlying the process. Recent research has shown that the fabrication process of a circuit is certainly an issue when measuring fault model performance [SHEN85]. However, it is also useful and informative to consider the functional limitations of fault models relative to the circuits themselves and independently of the technology chosen to realize them. Exhaustive simulation or simulation of particular test sets is one possible method that can be used to attack this sort of problem [HUGH86], [MILL88], [MILL89]. However, this approach is limited to relatively small samples of test sets due to otherwise exorbitant computation time requirements.

OBDDs for Symmetric Functions

Much of the analysis reported in this monograph has been achieved through the symbolic representation of Boolean functions. OBDDs have been conjectured to be an economical vehicle for Boolean functional manipulation, but just how efficient are they? There is no known canonical Boolean function representation which remains tractably bounded for any arbitrary switching function. However, the OBDD is linear in size for some functions which cannot be represented as compactly in other canonical forms. The exclusive-OR (XOR, ®) is an example of such a function. OBDD size has also been shown to grow exponentially for some functions regardless of the variable ordering. An example of this class of circuits is the integer multipler [BRYA91], although recent research has demonstrated techniques to address the problem [BURC91b].

Suggestions for Future Research

In the course of these investigations, many interesting questions have arisen that, due to time considerations, will remain unanswered in this research. This chapter will explore some of these questions in more detail.

Ordered Binary Decision Diagrams

In order to facilitate a detailed study of the perturbations of various fault models on the normal functioning of a given circuit, it is helpful to have the capacity to find all the tests for each fault in a fault set. One procedure to gather this information would be to inject each fault in the fault set, one at a time, and simulate all possible input patterns, noting when departures from the good machine outputs occur for each fault. An exhaustive method similar to the one just described was proposed in [BEH82]. Obviously, the time required for exhaustive approaches can become prohibitive quickly as circuit sizes grow.

Analyzing Test Performance with the ATPG Model

As we saw in the Introduction and again in Chapter 6, the quality of test sets is an important quantity, but one that is difficult to define and measure. Even if a suitable metric is defined, most existing methods to quantify the metrics fail to provide an acceptable level of statistical significance. In contrast, our method examines the properties of the entire set of one-vector-per-fault test sets. This number can be quite large.