Kenneth M. Butler

Minimizing power consumption in scan testing: pattern generation and DFT techniques

It is a well-known phenomenon that test power consumption may exceed that of functional operation. ICs have been observed to fail at specified minimum operating voltages during structured at-speed testing while passing all other forms of test. Methods exist to reduce power without dramatically increasing pattern volume for a given coverage. We present case study information on ATPG- and DFT-based solutions for test power reduction.

An analysis of power reduction techniques in scan testing

Power consumption during scan testing is becoming a concern. Circuit switching activity during scan shifting is high and results in high average and instantaneous power consumption. This paper presents a scheme for reducing power and provides analysis results on an industrial design.

Scan-based transition fault testing - implementation and low cost test challenges

The semiconductor industry as a whole is growing increasingly concerned about the possible presence of delay-inducing defects. There exist structured test generation and application techniques which can detect them, but there are many practical issues associated with their use. These problems are particularly acute when using low cost test equipment. In this paper, we describe an overall approach for implementing scan-based delay testing with emphasis on low-cost test.

REDO-random excitation and deterministic observation-first commercial experiment

For many years, non-target detection experiments have been simulated by using AND/OR bridges or gross delay faults as surrogates. For example, the defective part level can be estimated based upon surrogate detection when test patterns target stuck-at faults in the circuit. For the first time, test pattern generation techniques that attempt to maximize non-target defect detection have been used to test a real, 100% scanned, commercial chip consisting of 75 K logic gates. In this experiment, the defective part level for REDO-based patterns was 1,288 parts per million lower than that achieved by DC stuck-at based patterns generated using todays state of the art tools and techniques.

Defect-oriented testing and defective-part-level prediction

After an integrated circuit (IC) design is complete, but before first silicon arrives from the manufacturing facility, the design team prepares a set of test patterns to isolate defective parts. Applying this test pattern set to every manufactured part reduces the fraction of defective parts erroneously sold to customers as defect-free parts. This fraction is referred to as the defect level (DL). However, many IC manufacturers quote defective part level, which is obtained by multiplying the defect level by one million to give the number of defective parts per million. Ideally, we could accurately estimate the defective part level by analyzing the circuit structure, the applied test-pattern set, and the manufacturing yield. If the expected defective part level exceeded some specified value, then either the test pattern set or (in extreme cases) the design could be modified to achieve adequate quality. Although the IC industry widely accepts stuck-at fault detection as a key test-quality figure of merit, it is nevertheless necessary to detect other defect types seen in real manufacturing environments. A defective-part-level model combined with a method for choosing test patterns that use site observation can predict defect levels in submicron ICs more accurately than simple stuck-at fault analysis.

Power Supply Noise: A Survey on Effects and Research

As technology scales to 32 nm and functional frequency and density continue to rise, PSN effects, which can reduce a circuits noise immunity and could lead to failures, pose new challenges to chip manufacturers and foundries. This article provides an overview of low-power and delay testing, and surveys ongoing research for analyzing and dealing with PSN effects during delay test and timing analysis.

Test cost reduction through performance prediction using virtual probe

The virtual probe (VP) technique, based on recent breakthroughs in compressed sensing, has demonstrated its ability for accurate prediction of spatial variations from a small set of measurement data. In this paper, we explore its application to cost reduction of production testing. For a number of test items, the measurement data from a small subset of chips can be used to accurately predict the performance of other chips on the same wafer without explicit measurement. Depending on their statistical characteristics, test items can be classified into three categories: highly predictable, predictable, and un-predictable. A case study of an industrial RF radio transceiver with more than 50 production test items shows that a good fraction of these test items (39 out of 51 items) are predictable or highly predictable. In this example, the 3σ error of VP prediction is less than 12% for predictable or highly predictable test items. Applying the VP technique can on average replace 59% of test measurement by prediction and, consequently, reduce the overall test time by 57.6%.

Correlation of logical failures to a suspect process step

Traditional yield enhancement efforts have long relied on memory bitmapping techniques. With the industry marching toward system-on-a-chip technology, the importance of logic products has increased exponentially. This necessitates the development of innovative techniques to perform logic yield enhancement. In this paper the authors present a novel technique that can be used to perform logic yield enhancement. The paper concentrates on logic bitmapping at Texas Instruments. Results obtained from a few production samples of a graphics processor are also presented.

An empirical study on the effects of test type ordering on overall test efficiency

The order in which the various test types are applied can have an impact on the overall efficiency of the test operation. Furthermore, the speed at which the tests can be executed and the latency of defect detection are also important factors. In this paper, we evaluate an exhaustive set of test orderings over a variety of assumed execution parameters to analyze their effects on overall tester time consumption.

Facilitating rapid first silicon debug

Semiconductor manufacturers aim to deliver products to market within a short span of time in order to gain market share. There are several facets of introducing a product to market - design, manufacturing, first silicon debug, and ramp to volume. Of these, first silicon debug time contributes significantly towards reduced product cycle time if it can be kept short. In this paper, we discuss the infrastructure, design tools, test tools and debug tools required to achieve successful first silicon debug. We describe a production device that employs these infrastructure requirements, thereby demonstrating the advantages of following the guidelines. The paper also highlight the ill effects of not adhering to the guidelines.