Don-Gey Liu

Silicon-Controlled Rectifier for Electrostatic Discharge Protection Solutions With Minimal Snapback and Reduced Overshoot Voltage

An electrostatic discharge (ESD) protection structure constructed by the stacking of multiple anode gate-cathode gate directly connected silicon-controlled rectifiers (DCSCRs), fabricated in a 0.18-μm CMOS technology is reported in this letter. Two embedded diodes in the DCSCR dictate the turn-ON mechanism and hence give rise to a trigger voltage equal to twice the diodes turn-ON voltage. This approach enables the DCSCR to offer a diode-like transmission line pulsing IV characteristic with a minimal snapback and a SCR-like high-ESD robustness. At 25 °C, DCSCR has an acceptable nanoampere-level leakage current. Besides, it is verified that the DCSCR can significantly reduce overshoot voltage when stressed by very-fast-rising pulses. As such, an ESD clamp constructed by stacking a selected number of DCSCRs can offer a flexible trigger/holding voltage and is suitable for low and medium voltage ESD protection applications.

Investigations of Novel

A novel Γ-gate Al0.24Ga0.76As/In0.15Ga0.85As metal-oxide-semiconductor (MOS) high-electron-mobility transistor (MOS-HEMT) by using methods of ozone water oxidation and shifted exposure has been comprehensively investigated. Effective gate-length reduction, improved gate insulation, and formations of a field plate and a full surface passivation within the drain-source region are simultaneously achieved. The present Γ-gate MOS-HEMT has demonstrated superior device performances, including improvements of 523% (12.8%) in two-terminal gate-drain breakdown, 137% (36.1%) in on-state drain-source breakdown, 16.1% (11.8%) in maximum extrinsic transconductance (gm, max), 34.5% (9.7%) in intrinsic voltage gain (AV), 27.8% (16.2%) in power-added efficiency, 34.5% (19.8%) in minimum noise figure (NFmin) , and 28%/39.3% (11.4%/21.6%) in unity-gain cutoff frequency/maximum oscillation frequency (fT/fmax), as compared to a conventional Schottky-gate (MOS-gate) device fabricated upon the same epitaxial structure by using an identical optical mask set. Investigations of optimum extracted parasitics, small-signal device parameters, and high-temperature device characteristics at 300 K-450 K are also made in this work.

\Gamma

A CMOS amplifier with differential input and output was designed for very high common-mode rejection ratio (CMRR) and low offset. This design was implemented by the 0.35 µm CMOS technology provided by TSMC. With three stages of amplification and by balanced self-bias, a voltage gain of 80 dB with a CMRR of 130 dB was achieved. The related input offset was as low as 0.6 µV. In addition, the bias circuits were designed to be less sensitive to the power supply. It was expected that the whole amplifier was then more independent of process variations.This fact was confirmed in this study by simulation. With the simulation results, it is promising to exhibit an amplifier with high performances for biomedical applications.

-Gate MOS-HEMTs by Ozone Water Oxidation and Shifted Exposure Techniques

This study was aimed to design an electrocardiograph (ECG) system by the 0.35 μm CMOS technology. In this study, a two-stage operational amplifier was taken as the building block for the design of instrumentation amplifier and filters. In our measurement, excellent performance was verified by the fabricated chips.

Design a bioamplifier with high CMRR

In this paper, the charge pump (CP) based on a switches-in-source architecture is to be improved by gain-boosting amplifiers for phase-locked loops (PLLs). In our design, two differential amplifiers were employed in this CP to reduce the effect of the channel length modulation in MOS transistors. As a result, the up and down currents will be rather independent of the output voltage transformed by the capacitive low pass filter (LPF). This circuit was implemented using TSMC 0.18-µm CMOS technology and was investigated at a power supply of 1.8V. The measured mismatch was less than 1% for the output voltage ranging from 0.4 to 1.4V. This result is lower than that of the dynamic current-matching CP with feedback tuning on the same architecture. A comparison will be presented and discussed.

An ECG front-end circuit with single power supply

In this paper, an optimized pMOS-triggered bidirectional silicon-controlled rectifier (PTBSCR) fabricated in a 0.18-μm CMOS technology is proposed as a viable electrostatic discharge (ESD) protection solution. Capable of working under both the power-ON and power-OFF conditions, this structure is verified to provide bidirectional ESD protection performance superior to those reported in the literatures. Critical ESD parameters, such as the trigger voltage, holding voltage, and leakage current, can be flexibly adjusted via layout changes. With a low trigger voltage, a small ESD design window, a high robustness, and a small silicon area consumption, the PTBSCR is very suitable for low-voltage and low-power ESD protection applications.

Reduction of current mismatching in the switches-in-source CMOS charge pump

In this study, the charge pump (CP) was designed by gain-boosting amplifiers for lower mismatching. In this design two differential amplifiers were employed to reduce the effect of the channel length modulation in the transistors. This circuit was implemented by the 0.18-μm CMOS technology of TSMC at a power supply of 1.8 V. In our study, the measured mismatch was less than 1% for the output from 0.4 to 1.4 V which is very good for PLL applications.

Optimized pMOS-Triggered Bidirectional SCR for Low-Voltage ESD Protection Applications

In this study, the integrated circuit (IC) implemented by amorphous silicon (α-Si) thin-film transistors (TFTs) on the glass substrate was investigated. The target was aimed at the reliable design for the gate driver on the liquid crystal display (LCD) panels. In this design, the lifetime of TFT gate driver IC was tried to be improved. For practical considerations, single power supply voltage with single clocking scheme was specified in this TFT IC. In order to overcome the VTH shift of the vulnerable α-Si TFT, the dual pull-down structure was employed for critical parts. In this paper, both measurement and simulation results will be illustrated to demonstrate the performances of our circuits. With the obtained results, a system on a panel (SOP) is promising by α-Si TFT ICs.

Design for low current mismatch in the CMOS charge pump

This study focuses on a tracking technique for minimally invasive surgery to overcome the possible dangers by endoscopic techniques. We used the principles of electric fields to detect the position of the instrument. With a microprocessor board and a shareware tool known as Processing, a three-dimensional tracking system was developed so that the scalpel inside a patients body can be monitored by external receivers.

Integrated amorphous-Si TFT circuits for gate drivers on LCD panels

Designing a low-power high slew rate operational amplifier (OPA) is focused in this paper. There are three stages in this design. First, N and P complementary differential pairs (DP) were used to amplify input signals with low input offset. The second stage was a push-pull common source amplifier to boost the total voltage gain higher. In this stage, Miller feedback was employed to make the amplifier stable. The output stage adopted the super buffer technique to make this stage operated in a class AB mode. The amplitude of the output voltage was also pushed to the power supply rails at this output stage. In the design of the first and the last stages, we employed the flipped voltage follower (FVF) as the building block to pursue low quiescent bias current, large dynamic range and high slew rate at the same time. The output resistance at the output stage was reduced by local feedback. This circuit was designed based on TSMC 0.35μm CMOS technology. At present, the simulation exhibit good performance parameters, In the simulation results, we obtained a voltage gain over 130 dB with a unit-gain bandwidth larger than 80 MHz where its input offset voltage is smaller than 10 pV. The estimated slew rate was higher than 30 V/μs. This fact would promise our circuit to be a high performance operational amplifier for general applications.