Miin-Shyue Shiau

Design a bioamplifier with high CMRR

A CMOS amplifier with differential input and output was designed for very high common-mode rejection ratio (CMRR) and low offset. This design was implemented by the 0.35 µm CMOS technology provided by TSMC. With three stages of amplification and by balanced self-bias, a voltage gain of 80 dB with a CMRR of 130 dB was achieved. The related input offset was as low as 0.6 µV. In addition, the bias circuits were designed to be less sensitive to the power supply. It was expected that the whole amplifier was then more independent of process variations.This fact was confirmed in this study by simulation. With the simulation results, it is promising to exhibit an amplifier with high performances for biomedical applications.

Eliminating the Reverse Charge Sharing Effect in the Charge-Transfer-Switch (CTS) Converter

A novel voltage level controller for low-power charge pump converters will be presented in this paper. The proposed voltage level controller would react according to the pumped voltage in the charge-transfer-switch (CTS) converter. For the CTS circuit, the pumping operation would be degraded by the charge sharing effect in the auxiliary switch path. In this study, a voltage shifter was used as the voltage level controller to overcome this serious problem without consuming too much chip area. The simulation results showed that the converter can accept a rated input of 1.5V and generated an output up to 8V based on the TSMC 0.35-µm CMOS technology. The layout consumed an area of 125*160µm2. The highest output obtained in measuring the real chip was 5.5V which is primarily due to the limitation that the transistor could tolerated. The largest load was estimated as high as 6mW which is large enough for on-chip application.

Reduction of current mismatching in the switches-in-source CMOS charge pump

In this paper, the charge pump (CP) based on a switches-in-source architecture is to be improved by gain-boosting amplifiers for phase-locked loops (PLLs). In our design, two differential amplifiers were employed in this CP to reduce the effect of the channel length modulation in MOS transistors. As a result, the up and down currents will be rather independent of the output voltage transformed by the capacitive low pass filter (LPF). This circuit was implemented using TSMC 0.18-µm CMOS technology and was investigated at a power supply of 1.8V. The measured mismatch was less than 1% for the output voltage ranging from 0.4 to 1.4V. This result is lower than that of the dynamic current-matching CP with feedback tuning on the same architecture. A comparison will be presented and discussed.

Design for low current mismatch in the CMOS charge pump

In this study, the charge pump (CP) was designed by gain-boosting amplifiers for lower mismatching. In this design two differential amplifiers were employed to reduce the effect of the channel length modulation in the transistors. This circuit was implemented by the 0.18-μm CMOS technology of TSMC at a power supply of 1.8 V. In our study, the measured mismatch was less than 1% for the output from 0.4 to 1.4 V which is very good for PLL applications.

Integrated amorphous-Si TFT circuits for gate drivers on LCD panels

In this study, the integrated circuit (IC) implemented by amorphous silicon (α-Si) thin-film transistors (TFTs) on the glass substrate was investigated. The target was aimed at the reliable design for the gate driver on the liquid crystal display (LCD) panels. In this design, the lifetime of TFT gate driver IC was tried to be improved. For practical considerations, single power supply voltage with single clocking scheme was specified in this TFT IC. In order to overcome the VTH shift of the vulnerable α-Si TFT, the dual pull-down structure was employed for critical parts. In this paper, both measurement and simulation results will be illustrated to demonstrate the performances of our circuits. With the obtained results, a system on a panel (SOP) is promising by α-Si TFT ICs.

A high-slew rate rail-to-rail operational amplifier by flipped voltage followers

Designing a low-power high slew rate operational amplifier (OPA) is focused in this paper. There are three stages in this design. First, N and P complementary differential pairs (DP) were used to amplify input signals with low input offset. The second stage was a push-pull common source amplifier to boost the total voltage gain higher. In this stage, Miller feedback was employed to make the amplifier stable. The output stage adopted the super buffer technique to make this stage operated in a class AB mode. The amplitude of the output voltage was also pushed to the power supply rails at this output stage. In the design of the first and the last stages, we employed the flipped voltage follower (FVF) as the building block to pursue low quiescent bias current, large dynamic range and high slew rate at the same time. The output resistance at the output stage was reduced by local feedback. This circuit was designed based on TSMC 0.35μm CMOS technology. At present, the simulation exhibit good performance parameters, In the simulation results, we obtained a voltage gain over 130 dB with a unit-gain bandwidth larger than 80 MHz where its input offset voltage is smaller than 10 pV. The estimated slew rate was higher than 30 V/μs. This fact would promise our circuit to be a high performance operational amplifier for general applications.