Don MacMillen

Modeling and analysis of differential signaling for minimizing inductive cross-talk

Many physical synthesis tools interdigitate signal and power lines to reduce cross-talk, and thus, improve signal integrity and timing predictability. Such approaches are extremely effective at reducing cross-talk at circuit speeds where inductive effects are inconsequential. In this paper, we use a detailed distributed RLC model to show that inductive cross-talk effects are substantial in long busses associated with 0.18 micron technology. Simulation experiments are then used to demonstrate that cross-talk in such high speed technologies is much better controlled by re-deploying interdigitated power lines to perform differential signaling.

Managing on-chip inductive effects

With process technology and functional integration advancing steadily, chips are continuing to grow in area while critical dimensions are shrinking. This has led to the emergence of on-chip inductance to be a factor whose effect on performance and on signal integrity has to be managed by chip designers and has to be sometimes traded off against other performance parameters. In this paper, we cover several techniques to reduce on-chip inductance which in turn improve timing predictability and reduce signal delay and crosstalk noise. We present experimental results obtained from simulations of a typical high performance bus structure and a clock tree structure to examine the effectiveness of some of the different inductance reduction techniques.

Behavioral Synthesis Methodology for HDL-Based Specification and Validation

This paper describes a HDL synthesis based design methodology that supports user adoption of behavioral-level synthesis into normal design practices. The use of these techniques increases understanding of the HDL descriptions before synthesis, and makes the comparison of pre- and post-synthesis design behavior through simulation much more direct. This increases user confidence that the specification does what the user wants, i.e. that the synthesized design matches the specification in the ways that are important to the user. At the same time, the methodology gives the user a powerful set of tools to specify complex interface timing, while preserving a users ability to delegate decision-making authority to software in those cases where the user does not wish to restrict the options available to the synthesis algorithms.

An industrial view of electronic design automation

The automation of the design of electronic systems and circuits [electronic design automation (EDA)] has a history of strong innovation. The EDA business has profoundly influenced the integrated circuit (IC) business and vice-versa. This paper reviews the technologies, algorithms, and methodologies that have been used in EDA tools and the business impact of these technologies. In particular, we focus on four areas that have been key in defining the design methodologies over time: physical design, simulation/verification, synthesis, and test. We then look briefly into the future. Design will evolve toward more software programmability or some other kind of field configurability like field programmable gate arrays (FPGAs). We discuss the kinds of tool sets needed to support design in this environment.

ISIS: a system for performance driven resource sharing

The authors establish the importance of accurate bit-level area and delay modeling to the quality of circuits synthesized by resource sharing systems. They show that bit-level accuracy and integration with logic optimization are both desirable and feasible, since the added execution time is a small fraction of the total optimization time. The implementation of a resource sharing system called ISIS, which uses bit-level modeling, accounts for control delays, and optimizes sharing and resource performance selection together to generate high-quality circuits from register transfer language (RTL) descriptions, is described.<<ETX>>

A rank-one update method for efficient processing of interconnect parasitics in timing analysis

In this paper we presen t a rank-one update method for updating reduced-order models of interconnect parasitics when driv e resistances or load capacitances change, as commonly occurs during timing analysis. These rank-one updates are extremely inexpensive, do not require reexamining the original in terconnect netw ork, and most importantly are provably equivalent to rereducing the original netw ork. This abstract con tains the proof only for the case of varying the driver resistance, but examples are given to show that the exactness holds more generally. In particular, a cross-talk case is examined where the conductance matrix is singular.

Towards system-level electromagnetic field simulation on computing clouds

Cloud computing is a potential paradigm-shifter for system-level electronic design automation tools for chip-package-board design. However, exploiting the true power of on-demand scalable computing is as yet an unmet challenge. We examine electromagnetic (EM) field simulation on cloud platforms.

A Review of Hardware Synthesis Techniques

This chapter gives a general overview of hardware synthesis at the behavioral level, accompanied by a brief look at synthesis at other levels. It is intended to give the reader an idea of the capabilities and problems of behavioral synthesis as it stands, and to give the reader a set of starting points for further exploration of the literature.

Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies?

The notion of design for manufacturability is blurring the separation between the tasks of design and manufacture. In the era of nano-technologies, the description of the design rules has retreated back to an early stage form of many conditional cases and even an art. Thus, it is important to set the metrics for the manufacturability. However, who is going to be held accountable for the final outcomes? Should the designer, the EDA developer, the manufacture engineer, or a new breed of experts take the lead to tackle the problem?