Donald A. Draper

Flow-through latch and edge-triggered flip-flop hybrid elements

This paper describes a hybrid latch-flipflop (HLFF) timing methodology aimed at a substantial reduction in latch latency and clock load. A common principle is employed to derive consistent latching structures for static logic, dynamic domino and self-resetting logic.

A regenerative push-pull differential logic family

A new differential logic family is described. Complex Boolean functions are realized at one-third the propagation delay of static differential logic and up to 40% faster than existing dynamic logic. Using this logic, a 1.5 ns 64-bit adder is achieved in a 0.70 micron, 3.0 V process technology. The relative performance of this circuit technology at the fundamental power supply limit is also analyzed and discussed.<<ETX>>

A 0.25 mm x86 microprocessor with a 100 MHz socket 7 interface

The AMD-KG 3D MMX enabled processor is an enhanced follow-on to the AMD-KG MMX enabled processor. It is implemented in a 0.25 mm 2.1 V CMOS process to achieve a higher frequency of operation and 80 sq. mm die size. The K6-3D unit implements 19 floating-point (FP) vector operations to enhance 3D graphics and audio performance.