Hamid Partovi

Circuit techniques in a 266-MHz MMX-enabled processor

The AMD-K6 MMX-enabled processor is plug-compatible with the industry-standard Socket 7 and is binary compatible with the existing base of legacy X86 software. The microarchitecture is based on an out-of-order, superscalar execution engine using speculative execution. High performance and compact die size are achieved by using self-resetting, self-timed and pulsed-latch circuit design techniques in custom blocks and placed-and-routed blocks of standard cells. The 162 sq. mm die is fabricated on a 0.35-/spl mu/m, five-layer metal process with local interconnect. It is assembled into a ceramic pin grid array (PGA) using C4 flip-chip mounting. The processor functions at clock speeds up to 266 MHz.

Clock and synchronization networks for a 3GHz 64bit ARMv8 8-core SoC

This paper describes the clock distribution and synchronization network for a 64bit ARMv8 8-core microprocessor. Embedded in a SoC for cloud computing platforms, the processor is fabricated in a 40nm CMOS technology and operates at 3.0GHz. The system PLL has a measured rms jitter <;1psec and features dynamic frequency hopping for DVFS applications. In conjunction with a Star/H/Mesh topology, the clock distribution uses both CML and CMOS circuits to minimize period jitter and nominally achieves <;9psec of skew (2.7% of clock period). By using local Duty Cycle Adjustment circuits in each core to properly offset the clock duty cycle and ease timing critical paths, the processor performance improves by more than 5%. A simple probing circuit for high speed clock measurements can be used to monitor the high frequency excursions of the internal supply to counteract any timing violation that could occur. Finally an enhanced latch, which improves MTBF by up to 5 orders of magnitudes and thus is suited for high speed synchronization operations, is proposed.