Donald D. Parker

Quad pumped bus architecture and protocol

Decoder for decoding multiple instructions in parallel

Method and apparatus for generating a microinstruction responsive to the specification of an operand, in addition to a microinstruction based on the opcode, of a macroinstruction

Method for parallel steering of fixed length fields containing a variable length instruction from an instruction buffer to parallel decoders

Method and apparatus for aligning an instruction boundary in variable length macroinstructions with an instruction buffer

Method for state recovery during assist and restart in a decoder having an alias mechanism

Packing valid micro operations received from a parallel decoder into adjacent locations of an output queue

Enhanced highly pipelined bus architecture

Response and data phases in a highly pipelined bus architecture

Decoder having independently loaded micro-alias and macro-alias registers accessible simultaneously by one micro-operation