Donald Dibra

On the Origin of Thermal Runaway in a Trench Power MOSFET

In this paper, we investigate the origin of thermal runaway in the trench power MOSFET of a modern smart power IC technology. Experimental data on the temperature rise during power pulses show that the onset of thermal runaway depends on the biasing condition even if the power pulses have equal power dissipation. The beginning of thermal runaway in this work is denoted by the inflection point in the measured temperature data. For the experimental data points, the onset varies from 340 °C to 520 °C. Comparison of these experimental data with an analysis based on the stability factor shows very good agreement. The stability factor analysis demonstrates that, above the temperature compensation point (TCP), the driving force for thermal runaway is the thermally generated leakage current of the parasitic n-p-n bipolar transistor. The decrease of mobility and, hence, the MOS channel current above the TCP stabilizes the power MOSFET. In contrast, below the TCP, both the increase of the MOS channel current and the parasitic n-p-n bipolar transistor leakage current with temperature contribute to the thermal runaway.

ANSYS based 3D electro-thermal simulations for the evaluation of power MOSFETs robustness

Abstract Electro-thermal simulators are useful tools for introducing design and technology improvements during the design process of power MOSFET transistors. They are also helpful to predict the device behavior when operating under extreme electrical and temperature conditions and thus to predict its thermal robustness. Such simulators have to correctly take into account interactions between electrical and thermal behavior. In this paper we propose a new method to perform electro-thermal simulations of power MOSFETs using ANSYS simulator. The electrical and the thermal problem are fully coupled and iteratively solved using the FEM method. By means of a test chip, simulations and comparison with measurement have been performed in order to validate the simulation approach.

Fabrication of trench isolation and trench power MOSFETs in a smart power IC Technology with a single trench unit process

We report on using a single trench unit process for the trench isolation and for the trench power MOSFET of a common-drain smart power IC technology. The trench power MOSFET has a maximum specific on-resistance, (Ron⋅A), below 50mΩ-mm2 and a typical breakdown voltage, Vbr, of 95V. The trench isolation provides well isolation up to 90V. Using a single trench unit process for both devices results in low process costs. In addition both power and logic areas of a chip benefit from the trench process.

Seebeck difference - temperature sensors integrated into smart power technologies

In this work, difference - temperature (ΔT) sensors based on the Seebeck effect integrated into a common drain smart power MOSFET technology are presented. The sensors generate a voltage signal proportional to the ΔT. The highest Seebeck coefficient measured was 0.92 mV/K. This result was achieved with a p - doped silicon and n+ - doped poly silicon Seebeck ΔT sensor. Power MOSFETs with embedded Seebeck ΔT sensors are, to our knowledge, demonstrated for the first time.

Design of a test chip with small embedded temperature sensor structures realized in a common-drain power trench technology

A test chip with the purpose of thermal monitoring and analysis is implemented in a common-drain smart power trench MOSFET technology. For accurate evaluation of the junction temperature, small embedded sensor structures are introduced. One sensor is a bipolar transistor structure based on the linear temperature dependence of the base-emitter voltage. An existing solution is modified in order to fit small embedded NPN devices into the MOSFET cell array. The second one is a resistive sensor implemented in the p-doped bulk silicon mesa of the trench power MOSFET technology, offering substantial design benefits. Variations of the sensor resistance caused by electric field effects are explained and characterized. The described sensor structures are integrated as close as possible to the active heat-generation area of the MOSFET, thus providing accurate junction temperature measurements without adversely affecting MOSFET temperature distribution. Accuracy of the described test structures is verified by calibrated transient infrared thermography, taking into account temperature gradients between junction and chip surface caused by thick metallization layers. A special test chip variant with different compositions of top layers is presented for the purpose of verifying the introduced sensor concepts.

ESD induced functional upset in magnetic sensor ICs

This paper discusses the functional upset behavior of magnetic sensor ICs for automotive applications during ESD system level tests according to the ISO 10605 standard. The system level ESD functional upset robustness is presented for two different sensors, one with and one without a supply voltage drop capability (μ-short functionality).