Donald J. Samuels

Level-specific lithography optimization for 1-Gb DRAM

A general level-specific lithography optimization methodology is applied to the critical levels of a 1-Gb DRAM design at 175- and 150-nm ground rules. This three-step methodology-ruling out inapplicable approaches by physical principles, selecting promising techniques by simulation, and determining actual process window by experimentation-is based on process latitude quantification using the total window metric. The optimal lithography strategy is pattern specific, depending on the illumination configuration, pattern shape and size, mask technology, mask tone, and photoresist characteristics. These large numbers of lithography possibilities are efficiently evaluated by an accurate photoresist development bias model. Resolution enhancement techniques such as phase-shifting masks, annular illumination and optical proximity correction are essential in enlarging the inadequate process latitude of conventional lithography.

Single-level electric testsites for phase-shifting masks

The phase shifting mask technology has quickly progressed from the exploratory phase to a serious development phase. This requires high resolution measurement techniques to quantify experimental results to optimize the designs. This paper describes a set of electrical linewidth measurement testsites which covers all five representative lithographic features in combination of dark-field and light-field patterns, positive and negative resists. The testsites can investigate binary intensity mask, attenuated, alternating, subresolution-assisted, rim, unattenuated, edge, and covered edge phase shifting masks. All testsites can be used with a single-level wafer exposure. There is no need to remove extra shorts or opens induced by uncovered phase shifters.

Pattern transfer at k1=0.5: get 0.25-um lithography ready for manufacturing

In pattern transfer, as in any other method of information transfer, the output is usually a nonlinear function of the input. Lithography at the limit of resolution is an excellent object to demonstrate this. Printing structures smaller than 300 nm with a 4 X 0.5NA tool, the derivative of the pattern transfer function, or the ratio of pattern size variations on the wafer over pattern size variations at the mask level, is not a 4:1, as one would expect from the demagnification of the step and scan tool. In other words, below 300 nm, mask linewidth variations (for example butting errors of the mask writing tool) print at about twice their expected size. In the concept of the pattern transfer function, a mask defect is viewed as a localized variation in the linewidth of the mask. The printing of a mask defect therefore depends strongly on the slope of the pattern transfer function. Defects smaller than 200 nm on the mask already cause a significant linewidth variation on the wafer, if those defects are in a regular array of 250 nm lines/300 nm spaces or in 300 nm contact holes. Lithogrpahy in a manufacturing environment means to deliver the designed pattern over large areas using real masks. We discuss our strategies of how we try to minimize the influence of mask irregularities in 0.25 micrometers lithography for the development of the 256M DRAM. Although certain improvements are possible, the nonlinearity of the pattern transfer function at low k obviously demands extremely tight mask specifications beyond the limits of current tools and processes.

The Application of Deep UV Phase Shifted-Single Layer Halftone Reticles to 256 Mbit Dynamic Random Access Memory Cell Patterns

We have applied deep UV (DUV) halftone reticles, with a single layer absorptive shifter consisting of silicon nitride, to 256 Mbit dynamic random access memory (DRAM) critical levels, and have evaluated the resolution in those cell patterns. For the periodic line levels, halftone reticles were combined with off-axis illumination (OAI) techniques. Resolution capabilities were characterized not only with stepper exposures but also with direct aerial image measurement. For hole levels such the Storage Node and Bitline Contact, halftone reticles offered clear improvement with standard illumination as compared to conventional reticles. For line levels such the Isolation, Wordline and Bitline, dramatic improvement was obtained with the combination of halftone reticles and off-axis illumination.

Meeting critical gate linewidth control needs at the 65 nm node

With the nominal gate length at the 65 nm node being only 35 nm, controlling the critical dimension (CD) in polysilicon to within a few nanometers is essential to achieve a competitive power-to-performance ratio. Gate linewidths must be controlled, not only at the chip level so that the chip performs as the circuit designers and device engineers had intended, but also at the wafer level so that more chips with the optimum power-to-performance ratio are manufactured. Achieving tight across-chip linewidth variation (ACLV) and chip mean variation (CMV) is possible only if the mask-making, lithography, and etching processes are all controlled to very tight specifications. This paper identifies the various ACLV and CMV components, describes their root causes, and discusses a methodology to quantify them. For example, the site-to-site ACLV component is divided into systematic and random sub-components. The systematic component of the variation is attributed in part to pattern density variation across the field, and variation in exposure dose across the slit. The paper demonstrates our teams success in achieving the tight gate CD tolerances required for 65 nm technology. Certain key challenges faced, and methods employed to overcome them are described. For instance, the use of dose-compensation strategies to correct the small but systematic CD variations measured across the wafer, is described. Finally, the impact of immersion lithography on both ACLV and CMV is briefly discussed.

Electrical characterization of across-field lithographic performance for 256-Mbit DRAM technologies

Lithographic performance has typically been evaluated at a single point within the stepper field. However, this evaluation method does not completely provide the total lithographic performance on a chip because of variations introduced by the stepper as well as the reticle. In this paper, the evaluation method and characteristics of across-field performance are shown through the use of electrical line width measurements and exposure-defocus (ED) analysis. The across-field performance is analyzed by both the average process window and the common process window for two resolution enhanced photolithography techniques: phase-shifting mask (PSM) and off-axis illumination (OAI). The average process window corresponds to a single-point evaluation while the common process window includes all lithographic fluctuations across the field. Consequently, the common process window is much smaller than the average process window. Moreover, to consider the effect of mask critical dimension (CD) deviation on lithographic performance, a mask CD deviation enhancement factor (MEF) is introduced. By MEF correction, the contribution of mask CD deviation to common window degradation is obtained.

Process dependencies of optical proximity corrections

Optical Proximity Correction has emerged as an industry standard technique to reproduce the desired shapes on wafers as pattern dimensions are approaching the optical resolution limits. However secondary effects, if not properly controlled, may impede successful application of this technique. In order to better assess these factors we have divided the overall pattern formation process into several obvious components: The illumination system, mask, projection optics, resist system and finally etch processes. Each one of these components influences the optical proximity effects observed in the final pattern. The dependence of optical proximity corrections on the type of illumination is fairly well known and will only be touched on. Variations in the mask manufacturing process such as deviations of the mask critical dimension from its nominal value will be discussed. The type of e-beam exposure tool used to write the mask was found to have profound impact on optical proximity correction and therefore specifying the type of mask writing tool and sometimes even its writing mode to ensure reproducible results is required. Lens aberrations in the optical exposure tool and their impact were studied using aerial image simulations. Examples of optical proximity curves from different first generation tools show significant differences even between tools of the same type. Resist effects and the variations induced by modifying etch processes were investigated emphasizing that a fairly detailed control of the overall pattern formation process is necessary to successfully implement any OPC approach.

Good OPC, where will this drive mask CD tolerance and mask grid size

At low k1 factors, optical proximity correction (OPC) is used to correct line size such that what is delivered by the lithography process is closer to the design dimension than an uncorrected process would deliver. OPC is usually derived for perfect masks and exposures. Random variation of the mask critical dimension (CD), wafer exposure latitude, and wafer defocus are examined for their effects on an OPC mask. Expected CD variation in the aerial image is given for each of these variables. Examining these variables will also give insight as to how fine an OPC can realistically be obtained, and how fine a grid size is needed in the manufacture of the mask.

Image fidelity verification: contourIFV

The rapidly escalating complexity of resolution enhancement techniques (RET), now commonplace in leading edge lithography, requires accurate verification to avoid yield and performance problems on the patterned wafers. Model-based verification techniques that have been derived from optical proximity correction (OPC) obtain the required checking speed from sparse sampling of the layout at discrete evaluation points along the edges of layout patterns. This sparse sampling allows accurately calibrated models to be used for full chip checking applications. However, there is a demonstrated risk of missing significant patterning errors due to the sparse and edge-centric sampling of the layout. Grid-based simulation approaches which calculate the image on a fine grid over the entire layout space accurately detect patterning problems anywhere in the layout, but can be executed at reasonable runtimes for aerial image models only. The challenge for full-chip model-based verification of RET-enhanced layouts is, therefore, a trade-off between sparse, edge-centric simulation using accurate models versus simulations using approximate models over the entire layout space. This paper presents an approach, termed contourIFV, that has been demonstrated to overcome the aforementioned problems and has been shown to provide significant value in the verification of the RET and OPC prescription.

Challenge of 1-Gb DRAM development when using optical lithography

The traditional lithographic approach employed by the semiconductor industry has been to pursue use of advanced prototype optical exposure tools and resists. The benefits of doing so have been: (1) The lithographic process that is used in development more closely resembles the process that will in fact be used to manufacture the chip. (2) The cost of low K1 imaging (phase-masks, off-axis illumination, and surface imaging resist) can be avoided. However with the introduction of 1Gb-dynamic random access memory (DRAM) development, a paradigm shift is being experienced within the optical lithographic community. With 1Gb-DRAMs, the minimum feature size falls irreversibly below the optical wavelength used to image the feature. Such a situation will make low K1 factor imaging unavoidable. With 175 nm groundrules typical for first generation 1G-DRAMs, K1 factors near 0.4 will be common with 0.5 as an upper limit on advanced systems currently in development irrespective of optical wavelength. This paper will cover the selection process, experimental data, and problems encountered in defining and integrating the lithographic process used to support the critical mask levels on 1Gb-DRAM development. Factors considered include: resist, masks, and illuminations via both simulation and experiment. The simulations were conducted with both internal and externally developed software. The experimental data to be reviewed was generated using an experimental 0.6 NA KrF step and scan system provided by Nikon. The resist used is commercially available from the Shipley corporation.