Wilhelm Maurer

Process proximity correction using an automated software tool

The pattern transfer process from the chip layout data to the structures on the finished wafer consists of many process steps. Although desired, none of these steps is linear in all aspects of the pattern transfer. Approaching the process limits due to the ever-shrinking linewidth, the non- linearities of the pattern transfer clearly show up. This means, that one cannot continue the practice to summarize all process influences into one bias between the data used for mask making and the final chip structure. The correction of process non-linearities is a necessity. This correction is usually called optical proximity correction (OPC), although not all effects intended for correction are of optical origin and/or not all these are effects of the neighborhood. We therefore propose to use the term PPC (process proximity correction). This paper reports our experiences with the application of OPTISSIMO, a software tool developed to perform automatically OPC/PPC for full chip designs. First, we provide a definition of PPC, which in our view has to correct all non- linearities of the pattern transfer process from layout data to the final electrically measured structures. Then, the strategy of the OPC/PPC tool OPTISSIMO, a software package to perform PPC based on process simulation, is discussed. We focus on the data handling strategy and on the process modeling of the tool under evaluation. It is shown, that full chip OPC/PPC is practicable using a well-designed hierarchy management system combined with a pattern library. Finally, it is demonstrated, that a model-based OPC/PPC tool is by definition a process simulation tool, that is able to perform all simulation tasks (like defect printability) at reasonable accuracy.

Evaluation of a fast and flexible OPC package: OPTISSIMO

It is out of question, that current state-of-the-art lithography--printing 350 nm structures with i-line tools or 250 nm structures with DUV tools--needs to correct for proximity effects (OPC). Otherwise, all the well-known effects like line-end shortening, linewidth variation as a function of adjacent patterns, linewidth non-linearity, etc. will produce a pattern, that is significantly different from the intended design. In this paper, we report first evaluation results of OPTISSIMO, a software package for automatic proximity correction. Besides the ability to handle full-chip designs by preserving as much as possible of the original data-hierarchy, there are significant options for the user. A large number of choices can be made to balance between the precision of the correction and the complexity of the corrected design. The main target of our evaluations was to check for full-chip OPC for the gate level of a state-of-the-art design. This corresponds to print either linewidths in the 350 nm to 400 nm range with i-line lithography or 250 nm/300 nm linewidth with DUV lithography. Taking 400 nm i-line lithography as an example, 3% precision OPC which has been demonstrated. By using hierarchical data handling, it was shown, that even the data complexity of a 256 M DRAM can be managed within reasonable time.

Mask specifications for 193-nm lithography

It is now generally accepted, that optical lithography will be the mainstream approach to manufacture the I Gbit DRAM device generation with minimum features between I 80 nm (first working samples) and I 50 nm (projected fabrication). This development demands a considerable tightening of mask specifications. The printing of 180 nm I 150 nm features on a 193 nm-, 0.6 NA- tool is a highly non-linear pattern transfer process (ki = 0.56 I 0.47). Therefore, mask irregularities (defects, linewidth variations) will print easier than at larger dimensions. This paper presents results of full lithography simulations for the printability of mask linewidth variations and mask defects. Assuming, that the wafer linewidth error budget is shared between the lithography process and the mask as it is currently done (75% for the process, 25% for the mask), the linewidth uniformity on a mask has to be better than 12 nm for 180 nm designrules and better than 8 nm for 150 nm designrules. Masks have to have no defects larger than 100 nm resp. 70 nm (all those numbers are given at the 4x mask!). These numbers are almost a factor of 2 tighter than assumed in published mask specification roadmaps. Besides tightening the current specifications, the mask roadmap has to include other important parameters: We show, that the butting error of the mask writing tool, corner rounding, and the quality of the mask repair have substantial impact on the linewidth error on the wafer. Since mask defects print proportional to the squareroot of their area, the definition of mask repair quality has to be revised. Current mask repair processes cannot provide adequate repair quality. Since masks with these specifications are - in our point of view - not easy to make, we propose to reevaluate carefully the sharing of the wafer Iinewidth error budget. In other words, 193 nm lithography must dedicate a significantly larger portion of its (actually not so large) process window to the mask. Keywords: Optical Lithography, Mask Specifications, Mask Defect Printability, Mask Repair, Linewidth Error Budget

Pattern transfer at k1=0.5: get 0.25-um lithography ready for manufacturing

In pattern transfer, as in any other method of information transfer, the output is usually a nonlinear function of the input. Lithography at the limit of resolution is an excellent object to demonstrate this. Printing structures smaller than 300 nm with a 4 X 0.5NA tool, the derivative of the pattern transfer function, or the ratio of pattern size variations on the wafer over pattern size variations at the mask level, is not a 4:1, as one would expect from the demagnification of the step and scan tool. In other words, below 300 nm, mask linewidth variations (for example butting errors of the mask writing tool) print at about twice their expected size. In the concept of the pattern transfer function, a mask defect is viewed as a localized variation in the linewidth of the mask. The printing of a mask defect therefore depends strongly on the slope of the pattern transfer function. Defects smaller than 200 nm on the mask already cause a significant linewidth variation on the wafer, if those defects are in a regular array of 250 nm lines/300 nm spaces or in 300 nm contact holes. Lithogrpahy in a manufacturing environment means to deliver the designed pattern over large areas using real masks. We discuss our strategies of how we try to minimize the influence of mask irregularities in 0.25 micrometers lithography for the development of the 256M DRAM. Although certain improvements are possible, the nonlinearity of the pattern transfer function at low k obviously demands extremely tight mask specifications beyond the limits of current tools and processes.

The Application of Deep UV Phase Shifted-Single Layer Halftone Reticles to 256 Mbit Dynamic Random Access Memory Cell Patterns

We have applied deep UV (DUV) halftone reticles, with a single layer absorptive shifter consisting of silicon nitride, to 256 Mbit dynamic random access memory (DRAM) critical levels, and have evaluated the resolution in those cell patterns. For the periodic line levels, halftone reticles were combined with off-axis illumination (OAI) techniques. Resolution capabilities were characterized not only with stepper exposures but also with direct aerial image measurement. For hole levels such the Storage Node and Bitline Contact, halftone reticles offered clear improvement with standard illumination as compared to conventional reticles. For line levels such the Isolation, Wordline and Bitline, dramatic improvement was obtained with the combination of halftone reticles and off-axis illumination.

Benchmarking of software tools for optical proximity correction

The point when optical proximity correction (OPC) will become a routine procedure for every design is not far away. For such a daily use the requirements for an OPC tool go far beyond the principal functionality of OPC that was proven by a number of approaches and is documented well in literature. In this paper we first discuss the requirements for a productive OPC tool. Against these requirements a benchmarking was performed with three different OPC tools available on market (OPRX from TVT, OPTISSIMO from aiss and PROTEUS from TMA). Each of these tools uses a different approach to perform the correction (rules, simulation or model). To assess the accuracy of the correction, a test chip was fabricated, which contains corrections done by each software tool. The advantages and weakness of the several solutions are discussed.

Mask Specifications and OPC

The paper evaluates the implications of optical proximity correction (OPC) to mask specifications. This is done by simulation of 200 nm design rule structures using a conventional simulation tool for long lines and using the simulation module of an OPC-tool for more complicated design situations. Both tools were parameterized for a state-of-the- art lithography process using a 0.6 NA stepper and a chemically amplified resist. As long as OPC stays within reasonable limits (minimum feature size greater than 60% of the input pattern), the printability of a defect is about the same as in a dense line/space array. A defect of 200 nm size on a 4X mask produces change in linewidth of about 20 nm. Even for masks with subresolution structures, the increase of printability of mask defects is within 10% compared to un- corrected masks. However, simulation using resist parameters cannot reproduce the aerial image result, that masks with outriggers are less sensitive to mask linewidth variation than conventional masks.

Comparison of line shortening assessed by aerial image and wafer measurements

Increasing number of patterns per area and decreasing linewidth demand enhancement technologies for optical lithography. OPC, the correction of systematic non-linearity in the pattern transfer process by correction of design data is one possibility to tighten process control and to increase the lifetime of existing lithographic equipment. The two most prominent proximity effects to be corrected by OPC are CD variation and line shortening. Line shortening measured on a wafer is up to 2 times larger than full resist simulation results. Therefore, the influence of mask geometry to line shortening is a key item to parameterize lithography. The following paper discusses the effect of adding small serifs to line ends with 0.25 micrometer ground-rule design. For reticles produced on an ALTA 3000 with standard wet etch process, the corner rounding on them mask can be reduced by adding serifs of a certain size. The corner rounding was measured and the effect on line shortening on the wafer is determined. This was investigated by resist measurements on wafer, aerial image plus resist simulation and aerial image measurements on the AIMS microscope.

Good OPC, where will this drive mask CD tolerance and mask grid size

At low k1 factors, optical proximity correction (OPC) is used to correct line size such that what is delivered by the lithography process is closer to the design dimension than an uncorrected process would deliver. OPC is usually derived for perfect masks and exposures. Random variation of the mask critical dimension (CD), wafer exposure latitude, and wafer defocus are examined for their effects on an OPC mask. Expected CD variation in the aerial image is given for each of these variables. Examining these variables will also give insight as to how fine an OPC can realistically be obtained, and how fine a grid size is needed in the manufacture of the mask.

Integration of alternating phase-shift mask technology into optical proximity correction

The paper describes the extension of optical proximity correction (OPC), which is well established for conventional chromium-on-glass mask printing, to alternating phase shift masks (altPSM). Aerial image simulation of various situations of light-field and dark-field altPSM shows that the size of the phase shifter has a great impact on the printed critical dimension (CD). Especially layouts containing non-symmetric phase shifters or shifter sizes comparable to the nominal CD do not print on target. The application of optical proximity correction to the chromium structures between the phase shifters is capable to compensate for such effects. We demonstrate the added value of OPC using a simulation-based software tool for altPSM.