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Featured researches published by Donald L. Plumton.


Applied Physics Letters | 1991

Organometallic vapor phase epitaxy of AlGaAs/GaAs heterojunction bipolar transistors using tertiarybutylarsine

Tae Kim; Burhan Bayraktaroglu; T. Henderson; Donald L. Plumton

We have studied the use of tertiarybutylarsine (t‐BuAsH2) for organometallic vapor phase epitaxy (OMVPE) growth of AlGaAs/GaAs heterojunction bipolar transistors (HBTs). Good dc characteristics were achieved with t‐BuAsH2‐grown HBT structures, including common‐emitter current gains higher than 200 and 1000 for n‐p‐n and p‐n‐p structures, respectively. Near‐ideal current gain dependence on the collector current density was observed, indicating that the quality of AlGaAs was suitable for high‐performance HBTs. The microwave characteristics were also comparable to those of arsine‐grown HBTs. These results demonstrate that t‐BuAsH2 can successfully replace arsine for OMVPE growth of AlGaAs/GaAs HBT structures.


IEEE Transactions on Electron Devices | 1990

Planar AlGaAs/GaAs HBT fabricated by MOCVD overgrowth with a grown base

Donald L. Plumton; Jau-Yuann Yang; Francis J. Morris; Steven A. Lambert

A planar heterojunction bipolar transistor (HBT) with an AlGaAs emitter layer epitaxially grown onto a selectively defined grown base layer, where the base is grown with the collector as part of the original epi, is discussed. The transistors fabricated with this process exhibit good gain and output characteristics. Transistors with 7*7 mu m/sup 2/ emitters have exhibited a DC current gain of 10 to 1000 for base doping from 1*10/sup 19/ to 8*10/sup 17/ cm/sup 3/, respectively, and Early voltages >or=100 V. The propagation delay of 19-stage ring oscillators was 87 ps/gate. The transistor-fabrication process was designed to be manufacturable, and the planar nature of the transistor surface should permit large-scale integration with good yields. >


11th Annual Gallium Arsenide Integrated Circuit (GaAs IC) Symposium | 1989

GaAs BIJFET technology for linear circuits

Jau-Yuann Yang; Francis J. Morris; Donald L. Plumton; E.N. Jeffrey

BIJFET (bipolar junction FET) technology that integrates p-channel JFETs and n-p-n HBTs (heterojunction bipolar transistors) has been developed. The devices are fabricated using epi overgrowth of an AlGaAs layer onto a GaAs layer, which simultaneously results in the emitter on the base for the n-p-n and the gate on the channel for the PJFET. The individual HBTs and PJFETs showed better stability over a wide temperature range than comparable Si devices. A prototype op amp was designed to demonstrate the capability of the BIJFET process. A measured open-loop gain of 50 dB and an open-loop gain bandwidth product of 3.6 GHz compare favorably with those of Si monolithic BIJFET op amps.<<ETX>>


IEEE Transactions on Electron Devices | 1989

Comparison of self-aligned and non-self-aligned GaAs E/D MESFETs

Chang Feng Wan; H. Shichijo; William A. White; Rick Hudgens; Donald L. Plumton

The device characteristics and circuit performance of self-aligned GaAs E/D-MESFETs have been compared. The fabrication process for both devices is discussed. Electrical measurements across a 2-in wafer showed that an average self-aligned 40- mu m-wide, 1- mu m-long enhancement device has transconductance of 275+or-17 mS/mm, an intrinsic K-value of 16.3+or-2.7 mS/V, a series resistance of 0.88+or-0.1 Omega -mm, and a threshold deviation of 28 mV. Corresponding data for the non-self-aligned devices were 191+or-19 mS/mm, 10.3+or-1.4 mS/V, 1.2+or-0.2 Omega -mm, and 45 mV, respectively. An ECL-compatible 1-kb static RAM and a 4-kb static RAM were fabricated using both self-aligned and non-self-aligned processes for comparison. Using the self-aligned process, the power consumption of the 1-kb SRAM was 230 mW, compared to 530 mW for the non-self-aligned SRAM, while access times remained the same. Typical access times for self-aligned 4-b SRAM devices ranged from a minimum of 2.8 ns to a maximum of 3.8 ns. This 1-ns range is considerably less than that of a typical non-self-aligned device with 2.5 ns of access time scatter. >


Archive | 1993

Vertical field effect transistor and diode

Donald L. Plumton


Archive | 2008

Integrated circuit having interleaved gridded features, mask set and method for printing

Thomas J. Aton; Donald L. Plumton


Archive | 1992

Method to integrate HBTs and FETs

Donald L. Plumton; Francis J. Morris; Jau-Yuann Yang


Archive | 1990

Integrated circuit composed of group III-V compound field effect and bipolar semiconductors

Francis J. Morris; Donald L. Plumton; Jau-Yuann Yang; Han-Tzong Yuan


Archive | 1993

Epitaxial overgrowth method

Donald L. Plumton; Tae Seung Kim


Archive | 1995

Method of making a vertical FET using epitaxial overgrowth

Han-Tzong Yuan; Tae S. Kim; Donald L. Plumton

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