Donald R. Lampe

PULSED LASER DEPOSITION AND FERROELECTRIC CHARACTERIZATION OF BISMUTH TITANATE FILMS

Stoichiometric films of bismuth titanate, Bi4Ti3O12, have been grown for the first time by the technique of pulsed excimer laser deposition. Ferroelectric films were obtained at temperatures as low as 500 °C on Si(100), MgO(110), and Pt‐coated Si(100) substrates. Hysteresis measurements using a Pt‐coated Si sample yielded a saturation polarization value of about 28 μC/cm2, consistent with a randomly oriented titanate film structure. A preliminary metal‐insulator‐semiconductor sandwich structure of the form Bi4Ti3O12‐CaF2(100 A)‐Si was grown and used to examine polarization induced memory switching effects.

Characterization of charge-coupled device line and area-array imaging at low light levels

A cell design affording compacting of an active CCD sensor, interline shift sensor, transfer gate and stopper diffusion into 2-mil centers with 5-m aluminum lines and spacings in a 75 × 100 element array will be described. Coherent readout technique removes Nyquist noise and suppresses clock feedthroughs.

An electrically-reprogrammable analog transversal filter

A basic building block constructed with CCD and MNOS technologies will be described. The tap weights are analog and electrically reprogrammable to realize Fourier transformers, matched filters and correlators, and adaptive filters.

Pulsed Laser Deposition (PLD) of Oriented Bismuth Titanate Films for Integrated Electronic Applications

Abstract : In this paper we describe recent successes of growth of epitaxial bismuth titanate (BTO) films by pulsed laser deposition (PLD) suitable for electro-optic and electrical switching device structures, and fabrication of an improved gate structure for a ferroelectric memory FET (FEMFET). TEM and x-ray results indicate that excellent crystalline quality BTO films were achieved on LaAlO3. Polarization switching was demonstrated for BTO capacitors with epitaxial superconducting YBaCu3Oy as the lower electrode. Using an SiO2 buffer layer, a BTO/Si structure was fabricated and direct charge modulation in the Si by polarization reversal in the BTO was demonstrated.

UHV Processing of Ferroelectric Barium Magnesium Fluoride Films and Devices

Barium magnesium fluoride (BaMgF4) has recently emerged as a strong candidate for application as the gate dielectric in ferroelectric random access memory (FERRAM) devices with nondestructive readout (NDRO). In earlier papers we reported the successful growth of oriented BaMgF4 films on Si(100) and other substrates in a ultrahigh vacuum (UHV) system, as well as the results of the structural and electrical characterization of these ferroelectric films. In the present paper, we review some of the earlier results, and also examine the effect of variations in the growth temperature and various post-growth anneals on the stoichiometry, crystallinity, orientation, and electrical characteristics of the BaMgF4 films. Initial attempts at integrating the ferroelectric field-effect transistor (FEMFET) with the standard CMOS VLSIC processing, as well as the effect of adding a thin capping layer of SiO2 on the BaMgF4 will also be described.

BaMgF4 thin film development and processing for ferroelectric FETS

Abstract A ferroelectric memory field-effect transistor (FEMFET) where a ferroelectric thin film is incorporated directly into the gate structure of the transistor is attractive, because it provides not only nonvolatility, but also nondestructive readout (NDRO). At Westinghouse, we are currently developing a FEMFET using thin film barium magnesium fluoride (BaMgF4), a ferroelectric material that was discovered in 1969, but was not fabricated in thin film form until 1989. The BaMgF4 films are grown by evaporation in an ultrahigh vacuum (UHV) chamber on clean Si(100). The natural tendency of these films to grow with the ferroelectric a-axis in the Si(100) plane has been overcome to obtain more random orientation with larger reversible polarization perpendicular to the film. A capping layer (SiO2) has been found to be essential for process integrability of these BaMgF4 films. Ti-W metallization produced only a slight reduction in the capacitance-voltage (C-V) memory window. Switching speed of these films has...

A nonvolatile charge-addressed memory (NOVCAM) cell

The combination of CCD and MNOS devices for signal transfer and nonvolatile storage has been discussed by several workers 1–3. In the initial attempt to combine these structures 1 the MNOS storage site was located inside a stepped dielectric, 2φ, CCD shift register. Certain problems were encountered such as inadequate charge handling capability which resulted in poor write characteristics, ineffective write/inhibit operation since high voltage clocks (for good transfer efficiency) caused spurious write operation, poor read operation due to the large access time to first bit and small detection window, and degraded memory retention caused by a small write window and read-disturb effects. To alleviate these problems a compact, nonvolatile, charge-addressed memory (NOVCAM) cell was introduced 2 for block oriented random access memory (BORAM) applications. The NOVCAM cell is composed of a CCD shift register and a thin-oxide MNOS memory structure in parallel with the register to provide separate locations for signal address and storage. Charge is transferred from the CCD shift register to the MNOS structure with a transfer gate φ T which results in a collapse of the surface potential beneath the MNOS structure. Once the surface potential is collapsed, the oxide electric field strength increases and the tunneling of signal charge commences from the surface channel into deep traps located near the Si0 2 /Si 3 N 4 interface. The read-out is nondestructive (NDRO) and accomplished through the control action of the MNOS surface potential which gates the parallel charge injection from a P+ source diffusion into the CCD shift register.

Pulsed laser deposition of ferroelectric bismuth titanate

Stoichiometric bismuth titanate films were prepared on MgO, Si, and Pt-coated Si by the technique of pulsed excimer laser deposition. This technique is a high-energy process with the potential to form the ferroelectric phase at a lower temperature than by sputtering. Fiber textured films were obtained on MgO [110] with preferred c-axis orientation. Polycrystalline films were obtained on Si [100] and Pt-coated Si at a temperature as low as 500 degrees C. The estimated saturation polarization and coercive field measured for the films were 28.0 mu C/cm/sup 2/ and 200 kV/cm, respectively. Also important from an integrated silicon device point of view, the as-deposited films had few particulates and were crack-free without the need for a postdeposition anneal. Results of attempts to integrate the films prepared in this manner in a FET memory structure are outlined.<<ETX>>

Integration of UHV-grown ferroelectric films into nonvolatile memories

Experimental evidence collected and evaluated during the preliminary development of a FEMFET (ferroelectric memory FET) is presented. In addition to microstructural characterization and ferroelectric polarization measurements, capacitance-voltage (C-V) measurements of several BaMgF/sub 4/ films grown under various conditions (ultrahigh vacuum (UHV) vs. regular high vacuum) were performed. The C-V hysteresis loops of the UHV-grown films showed that not only can the semiconductor conductivity be modulated directly through polarization reversal in the fluoride film, but also the saturated memory window is virtually undiminished after 10/sup 7/ switching cycles. The initial steps used to develop the integration of the FEMFET into a certified 1- mu m CMOS VLSIC process and the results achieved to date are reported.<<ETX>>

A Viable NDRO FERRAM Dielectric Structure

Research efforts at Westinghouse over the past three years have demonstrated the use of multi-layered gate dielectric structures in integrated ferroelectric memory field-effect transistors (FEMFETs). Such gate structures include both ferroelectric films and high-quality non-ferroelectric insulating buffer-andcapping layers. These layers, which usually comprise SiO, and Si,N,, perform vital functions by (a) suppressing tunneling/ trapping of charge from the silicon into the ferroelectric film, (b) inhibiting chemical interaction at the interface with the ferroelectric layer, (c) enhancing the breakdown strength and electrical stabilty of the gate structure, and (d) passivating the gate dielectric against subsequent high-temperature processing.