Marvin H. White

On the go with SONOS

Advancements in scaling gate insulators for MOS transistors permit low-voltage, silicon-oxide-nitride-silicon (SONOS) nonvolatile semiconductor memories (NVSMs) for a wide range of applications. The continued scaling of SONOS devices offers improved performance with a small cell size, single-level polysilicon with low voltage, fast erase/write, improved memory retention, increased endurance, and radiation hardness. In this article, we discuss scaled SONOS devices, SONOS memory technology, and some SONOS NVSM applications.

Modeling of transconductance degradation and extraction of threshold voltage in thin oxide MOSFET's

Abstract In this paper, we discuss the low-drain voltage transconductance behavior of the MOSFET due to surface mobility variation, interface states and small geometry, and its application in threshold voltage determination. We modify the Pao-Sah drain current model to incorporate a mobility model and obtain 3% accuracy from subthreshold to very strong inversion for a wide range of substrate biases. The effects of non-ideal scaling, finite inversion layer thickness, surface roughness mobility degradation under high normal electric fields and interface states on the transconductance behavior are discussed. We observe the peak transconductance increases with substrate bias in short-channel devices and decreases with substrate bias in long-channel devices. Finally, we show the threshold voltage can be determined from the gate voltage at which the rate of transconductance change ( ∂g m ∂V GS ) is a maximum. This threshold voltage is identifiable with a known band-bending (surface potential) of the substrate (φ s ⋍ 2φ F + V SB ) , from which the band-bending at all gate biases can be calculated. The transconductance change (TC) method is insensitive to device degradations (e.g. mobility, series resistance, hot-carrier) in contrast to the conventional method of linear extrapolation to zero drain current.

Charge retention of scaled SONOS nonvolatile memory devices at elevated temperatures

Abstract The charge retention characteristics in scaled SONOS nonvolatile memory devices with an effective gate oxide thickness of 94 A and a tunnel oxide of 15 A are investigated in a temperature range from room temperature to 175°C. Electron charge decay rate is sensitive to the temperature, whereas hole charge decay rate remains essentially constant. Based on experimental observations and an amphoteric trap model for nitride traps, an analytical model for charge retention of the excess electron state is developed. Using this thermal activated electron retention model, the trap distribution in energy within the nitride film is extracted.

Theory and application of charge pumping for the characterization of Si-SiO/sub 2/ interface and near-interface oxide traps

A generalized charge pumping model has been developed which extends the use of charge pumping from a study of traps at the Si-SiO/sub 2/ interface to a study of traps in the oxide. The analytical model, based on tunneling theory, allows the spatial distribution of near-interface oxide traps to be determined from variable frequency charge pumping data. Profiling of near-interface oxide traps in irradiated MOSFETs as well as SONOS nonvolatile memory devices is presented. >

Design considerations in scaled SONOS nonvolatile memory devices

Abstract Scaling the programming voltage, while still maintaining 10-year data retention time, has always been a big challenge for polysilicon–oxide–nitride–oxide–silicon (SONOS) researchers. We describe progress in the design and scaling of SONOS nonvolatile memory devices. We have realized −9+10 V (1 ms) programmable SONOS devices ensuring 10-year retention time after 107 erase/write cycles at 85°C. Deuterium anneals, applied in SONOS device fabrication for the first time, improves the endurance characteristics when compared with traditional hydrogen or forming gas anneals. We introduce scaling considerations and process optimization along with experiments and SONOS device characterization. A field programmable gate array-based measurement system is described for the dynamic characterization of SONOS nonvolatile memory devices.

Observation of near-interface oxide traps with the charge-pumping technique

In studies of MOS devices with the charge pumping technique, the authors have encountered a low-frequency increase in the charge recombined per cycle, which they attribute to the charging and discharging of traps located within a tunneling distance of the Si-SiO/sub 2/ interface, i.e., near-interface oxide traps. MOS devices subjected to ionizing radiation as well as ultrathin tunnel oxide polysilicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory devices possess a high density of near-interface oxide traps. When the charge recombined per cycle is examined as a function of frequency, a breakpoint is observed at a particular frequency with an inverse equivalent to a trap-to-trap tunneling time constant.<<ETX>>

A low voltage SONOS nonvolatile semiconductor memory technology

The triple-dielectric polysilicon-blocking oxide-silicon nitride-tunnel oxide-silicon (SONOS) structure is an attractive candidate for high density E/sup 2/PROMs suitable for semiconductor disks and as a replacement for high-density dynamic random access memories (DRAMs). Low programming voltages (5 V) and high endurance (greater than 10/sup 7/ cycles) are possible in this multidielectric technology as the intermediate Si/sub 3/N/sub 4/ layer is scaled to thicknesses of 50 /spl Aring/. The thin gate insulator and low programming voltage enable the scaling of the basic memory cell and associated complementary metal-oxide-semiconductor (CMOS) peripheral circuitry on the memory chip. A SONOS 1TC memory cell is proposed in a NOR architecture with a cell area of 6F/sup 2/ where F is the technology feature size. A 0.20 /spl mu/m feature size permits a 1TC area of 0.24 /spl mu/m/sup 2/ for advanced 1-Gb nonvolatile semiconductor memory chips. A physical model is presented to characterize the erase/write, retention and endurance properties of the nonvolatile semiconductor memory (NVSM) SONOS device.

Charge transport and storage of low programming voltage SONOS/MONOS memory devices

Abstract In this paper, a model based on two carrier conduction (electrons and holes) at both injecting boundaries (semiconductor bulk and gate electrode) is introduced to interpret the ERASE/WRITE characteristics of scaled SONOS devices. The amphoteric statistics describe the positive and negative charging of the deep-level traps in the nitride “memory” layer. Scaled SONOS/MONOS (polysilicon-oxide-nitride-oxide-semiconductor)/(metal-oxide- nitride-oxide-semiconductor) transistors and capacitors with the bottom (‘tunnel’) oxide layer thickness around 20 A, the final nitride layer thickness below 100 A, and the top (‘blocking’) oxide layer thickness between 35–50 A, have been fabricated and characterized. The results of the model are consistent with the experimental data, which permits physical insight into the mechanisms of charge injection, transport and storage during the ERASE/WRITE operation. Lattice imaging electron microscopy (TEM), ellipsometry, electrical capacitance, and chemical etchback techniques have been used to determine scaled SONOS/MONOS material parameters. The linear voltage ramp technique, which simultaneously measures the flatband voltage shift and separates the charges at the injecting boundary, and the dynamic pulse techniques of flatband tracking and threshold monitoring, which measure ERASE/WRITE, retention and endurance operations, have been employed to electrically characterize the scaled SONOS/MONOS devices. We have demonstrated a differential, saturated ERASE/WRITE flatband shift of 3.8 V with a ±5 V programming voltage for scaled-down SONOS/MONOS devices with dimensions of 20 A for the tunnel oxide, 50 A for the nitride, and 35 A for the blocking oxide. With ±5 V saturated ERASE/WRITE programming voltages and 10 6 ERASE/WRITE cycles, extrapolated retention gives a projected 10 year 0.5 V memory window at room temperature.

A CMOS-integrated 'ISFET-operational amplifier' chemical sensor employing differential sensing

The ISFET (ion-sensitive field-effect transistor) pH sensor is first matched with a MOSFET at the differential input stage of a CMOS operational amplifier (called the ISFET-operational amplifier) to cancel out the temperature sensitivity. Then, the output of an ISFET-operational amplifier with a Ta/sub 2/O/sub 5//SiO/sub 2/ gate (58-59 mV/pH) ISFET is differentially amplified against the output of another on-chip ISFET-operational amplifier with a SiO/sub x/N/sub y//Si/sub 3/N/sub 4//SiO/sub 2/ gate ISFET (18-20-mV/pH). An on-chip noble metal counterelectrode serves as the electrical contact to define the electric potential of the electrolyte. No external reference electrode is required. The difference measurement technique achieves (1) common-mode rejection of the solution potential, and (2) relaxation of the requirement that the on-chip reference electrode be ideal. The CMOS-compatible ISFET process is modified from a standard self-aligned polysilicon gate CMOS process with minimal process redesign. The standard CMOS sequence is unaltered until the contact windows are opened. The complete sensor has 40-43-mV/pH pH sensitivity and demonstrates common-mode rejection to ambient light and noise from the electrolyte. >

Characterization of SONOS oxynitride nonvolatile semiconductor memory devices

Abstract We present results on scaled silicon–oxide–nitride–oxide–silicon (SONOS) nonvolatile semiconductor memory devices with oxygen-rich ‘oxynitride’ charge storage layers. SONOS devices are designed specifically for high-density EEPROMs operating at high temperatures. We describe scaling considerations and process optimization to achieve low-voltage operation (+7 V write for 2.5 ms/−7 V erase for 7.5 ms) with 10-year retention at 150 °C. Memory transistors are programmed, erased, and read at elevated temperatures in order to observe thermal excitation of electrons from traps in oxynitride charge storage layers. The density of traps in the oxynitride is extracted using charge decay rates of programmed transistors at elevated temperatures. Trap density profiles for oxynitride films are compared with trap density profiles for silicon-rich nitride films.