Dong-Hwa Kwak

Integration Technology of 30nm Generation Multi-Level NAND Flash for 64Gb NAND Flash Memory

Multi-level NAND flash memories with a 38 nm design rule have been successfully developed for the first time. A breakthrough patterning technology of Self Aligned Double Patterning (SADP) together with ArF lithography is applied to three critical lithographic steps. Other key integration technologies include low thermal budget ILD process and twisted bit-line contact for excellent isolation between adjacent bit lines. Hemi-Cylindrical FET (HCFET) together with charge trapping memory cell of Si/SiO2 /SiN/Al2O3/TaN (TANOS) was found to be effective in sufficing various electrical requirements of 30 nm generation flash cells. Finally, MLC operation is successfully demonstrated with flash cells of 8 Gb density in which all the technologies aforementioned are combined.

Highly manufacturable 90 nm DRAM technology

A 90 nm DRAM technology has been successfully developed using 512 Mb DRAM for the first time. ArF lithography is used for printing critical layers with resolution enhancement techniques. A novel gap-filling technology using spin coating oxide is developed for STI and ILD processes. A diamond-shaped storage node is newly developed for large capacitor area with better mechanical stability. A CVD Al process can make the back-end metallization process simple and easy. A dual gate oxide scheme can provide independent optimization for memory cell transistor and periphery support device so that the off-state leakage current of the cell transistor can be maintained below 0.1 fA.

Development of 38nm Bit-Lines using Copper Damascene Process for 64-Giga bits NAND Flash

In order to develop high density NAND flash device, the increased number of cell strings for 1 page buffer forces to form a long bit-line with low sheet resistance, as well as low parasitic capacitance between bit-lines. In this paper, we secured a copper damascene process to form 38 nm bit-lines with 76 nm pitch using SADP (self-aligned double patterning) process. The methods to minimize the sheet resistance and to suppress the parasitic capacitance were explained on NAND flash device with 38 nm node technology.

A DRAM technology using MIM BST capacitor for 0.15 /spl mu/m DRAM generation and beyond

Recently, 1 Gb DRAM based on the 0.18 /spl mu/m technology node (generation) and 0.15 /spl mu/m technology node for 4 Gb DRAM have been successfully demonstrated. These two technology generations are based on MIS capacitors using Ta/sub 2/O/sub 5/ dielectric. The extension of Ta/sub 2/O/sub 5/ MIS capacitors below 0.15 /spl mu/m technology is considered to be difficult due to insufficient cell capacitance. It is widely accepted that the MIM capacitor using high dielectric constant material is inevitable for 0.15 /spl mu/m technology and beyond. Although many studies to use high dielectric material have been reported, those studies are not adequate for 0.15 /spl mu/m technology and beyond because most of the studies are either based on a simple capacitor module process or based on large feature size design rules. In this paper, for the first time, a DRAM technology using BaSrTiO/sub 3/ (BST) MIM capacitors is developed with 0.15 /spl mu/m technology.

Comparison of double patterning technologies in NAND flash memory with sub-30nm node

Fine patterning technologies - E-beam lithography, SPT (Spacer Patterning Technology) and SaDPT (Self aligned Double Patterning Technology)-have been introduced to develop a single unit of nano-scale MOSFET. However, in order to achieve manufacturable high density NAND Flash memories, the merits and demerits of each technology should be considered in three points of view: device characteristics, process controllability and mass production. In this paper, we suggest the appropriate technology for particular cell types, CTF(Charge Trap Flash) cell, floating poly-Si gate cell, and for process steps such as active, gate and bit-line.

Smallest Bit-Line Contact of 76nm pitch on NAND Flash Cell by using Reversal PR (Photo Resist) and SADP (Self-Align Double Patterning) Process

For the scaling down of design rule to develop the high density NAND flash device, the reduced active area forces to form a small bit-line contact with the low contact-resistance, as well as the low junction leakage current due to the borderless contact. In this paper, we propose a novel process to make 38 nm small size contact with 76 nm pitch by using the reversal PR (photo resist) and SADP (self-align double patterning) process. The methods to minimize the contact resistance and to suppress the junction leakage current were explained on NAND flash device with 38 nm node technology.

Modeling of Re-Sputtering Induced Bridge of Tungsten Bit-Lines for NAND Flash Memory Cell with 37nm Node Technology

As the design rule is scaled down, the electrical isolation of metal lines becomes critical. In a high density flash memory with 37nm (pitch=74nm) technology, the threshold voltage shift of ∼0.3V is found to be caused by tungsten micro-bridge between adjacent bit-lines. Simulations and experimental data showed that tungsten re-sputtering is occurred during the deposition of HDP (High Density Plasma)-SiO2 used as the filling dielectric between tungsten bit-lines. In this paper, the model for the tungsten re-sputtering is presented. The plasma simulations are performed to investigate the effects of process factors of HDP-SiO2 deposition on the formation of micro-bridge using in-house tool, PIE simulator.

A novel cell-STP (storage node through plate node) cell-technology for multigigabit-scale DRAM and logic-embedded DRAM generations

A novel cell technology has been developed to overcome process issues related with successful downscaling of a DRAM memory cell and to produce a reliable and manufacturable cell. Storage node in the proposed cell is formed in a self-aligned manner through the plate node after the formation of plate node and capacitor dielectric. Considering the scalability of the novel cell and experimental results showing the charge storage capacitance of 25fF/cell, leakage current less than 1fA/cell, and excellent time-to-dielectric breakdown characteristics, it is expected that this novel cell technology can be a promising candidate for the 1Gb DRAM and beyond as well as logic-embedded DRAM.