B.J. Hwang

Integration Technology of 30nm Generation Multi-Level NAND Flash for 64Gb NAND Flash Memory

Multi-level NAND flash memories with a 38 nm design rule have been successfully developed for the first time. A breakthrough patterning technology of Self Aligned Double Patterning (SADP) together with ArF lithography is applied to three critical lithographic steps. Other key integration technologies include low thermal budget ILD process and twisted bit-line contact for excellent isolation between adjacent bit lines. Hemi-Cylindrical FET (HCFET) together with charge trapping memory cell of Si/SiO2 /SiN/Al2O3/TaN (TANOS) was found to be effective in sufficing various electrical requirements of 30 nm generation flash cells. Finally, MLC operation is successfully demonstrated with flash cells of 8 Gb density in which all the technologies aforementioned are combined.

Development of 38nm Bit-Lines using Copper Damascene Process for 64-Giga bits NAND Flash

In order to develop high density NAND flash device, the increased number of cell strings for 1 page buffer forces to form a long bit-line with low sheet resistance, as well as low parasitic capacitance between bit-lines. In this paper, we secured a copper damascene process to form 38 nm bit-lines with 76 nm pitch using SADP (self-aligned double patterning) process. The methods to minimize the sheet resistance and to suppress the parasitic capacitance were explained on NAND flash device with 38 nm node technology.

Fabrication and characteristics of novel load PMOS SSTFT (Stacked Single-crystal Thin Film Transistor) for 3-Dimensional SRAM memory cell

The PMOS SSTFT (stacked single-crystal thin film transistor) is developed for achieving the smallest SRAM cell size, such as 45F/sup 2/, and low power mobile applications with the single crystallization technology of the Si thin films on the insulators. The electrical properties of the SSTFT load pMOS are comparable to those of bulk Si Tr. or SOI Tr. For example, Ion/Ioff ratio is nearly 10/sup 7/ and sub-threshold swing is 150 mV/dec. The SNM(Static Noise Margin) value is 650 mV at Vdd=2.0 V and the SSTFT load pMOS lifetime under the HElP stress is over 10 years at 3.0 V operation voltage. The novel S/sup 3/ (stacked single-crystal Si) SRAM cell used the SSTFT pMOS as the load pMOS which is successfully fabricated.

Ultra-low power and high speed SRAM for mobile applications using single Poly-Si gate 90 nm CMOS technology

High speed and ultra-low power SRAM using single gate CMOS technology was developed. The drive currents of NMOSFET and PMOSFET were 410 /spl mu/A//spl mu/m and 205 /spl mu/A//spl mu/m, respectively. The random access time of 17 ns at 1.65 V operation voltage was achieved for the first time in low power application by the reduction of loading capacitance. Standby current was less than 15 /spl mu/A/chip. The highly manufacturable compact cell of 0.84 /spl mu/m/sup 2/ area was integrated using PR (photo resist) flow technology and novel contact layout.

Highly manufacturable 32 Mb ULP-SRAM technology by using dual gate process for 1.5 V Vcc operation

For 1.5 V low Vcc operation and high performance, a full-CMOS ultra low power (ULP) SRAM using dual gate and Co salicide technology was developed. We evaluated the new technology including (i) 0.11 /spl mu/m fine patterning implemented by phase shift mask (PSM) and optical proximity correction (OPC), (ii) dual gate CMOS transistors with thin gate oxide, (iii) improvement of the Co salicide process to minimize leakage current, including ultra-shallow junction and rapid thermal annealing (RTA) processing. The results have been achieved on a 32 Mb high density 6 T ULP-SRAM cell.

Comparison of double patterning technologies in NAND flash memory with sub-30nm node

Fine patterning technologies - E-beam lithography, SPT (Spacer Patterning Technology) and SaDPT (Self aligned Double Patterning Technology)-have been introduced to develop a single unit of nano-scale MOSFET. However, in order to achieve manufacturable high density NAND Flash memories, the merits and demerits of each technology should be considered in three points of view: device characteristics, process controllability and mass production. In this paper, we suggest the appropriate technology for particular cell types, CTF(Charge Trap Flash) cell, floating poly-Si gate cell, and for process steps such as active, gate and bit-line.

Smallest Bit-Line Contact of 76nm pitch on NAND Flash Cell by using Reversal PR (Photo Resist) and SADP (Self-Align Double Patterning) Process

For the scaling down of design rule to develop the high density NAND flash device, the reduced active area forces to form a small bit-line contact with the low contact-resistance, as well as the low junction leakage current due to the borderless contact. In this paper, we propose a novel process to make 38 nm small size contact with 76 nm pitch by using the reversal PR (photo resist) and SADP (self-align double patterning) process. The methods to minimize the contact resistance and to suppress the junction leakage current were explained on NAND flash device with 38 nm node technology.

Modeling of Re-Sputtering Induced Bridge of Tungsten Bit-Lines for NAND Flash Memory Cell with 37nm Node Technology

As the design rule is scaled down, the electrical isolation of metal lines becomes critical. In a high density flash memory with 37nm (pitch=74nm) technology, the threshold voltage shift of ∼0.3V is found to be caused by tungsten micro-bridge between adjacent bit-lines. Simulations and experimental data showed that tungsten re-sputtering is occurred during the deposition of HDP (High Density Plasma)-SiO2 used as the filling dielectric between tungsten bit-lines. In this paper, the model for the tungsten re-sputtering is presented. The plasma simulations are performed to investigate the effects of process factors of HDP-SiO2 deposition on the formation of micro-bridge using in-house tool, PIE simulator.

Photoresist flow simulation using the viscous flow model

The PR (photoresist) flow process, applied to contact patterning, is difficult to predict and optimize because a process model does not exist. In this paper, the PR flow simulation method, using a viscous flow model, is developed and applied to examine the effect of initial shape and process conditions on the PR flow phenomena. In addition, this model is used to optimize the layout with the various contacts in the real pattern. This PR flow model, linked to lithography and etch ones, can predict and optimize the contact patterning process in cell, periphery, and TEG (test element group) areas and analyze defects, considering the pre-/post-processes, systematically.

Novel 3-dimensional 46F/sup 2/ SRAM technology with 0.294um/sup 2/ S/sup 3/ (stacked single-crystal Si) cell and SSTFT (stacked single-crystal thin film transistor)

We have realized a 46F/sup 2/ SRAM cell size of 0.294 /spl mu/m/sup 2/ with 80 nm technology and single stack S/sup 3/ cell technology. SSTFTs and vertical node contacts are major keys in the S/sup 3/ cell technology. The stacked single crystal silicon thin film is developed for the load pMOS SSTFT of the S/sup 3/ SRAM cell. The load pMOS SSTFT is stacked on ILD to reduce the SRAM cell size. Fully working 64 Mbit SRAM is achieved by this S/sup 3/ cell technology. The basic reliability of SSTFT, with 80 nm length, is also investigated in this study.