Dong Hyun Baik

A yield improvement methodology using pre- and post-silicon statistical clock scheduling

In deep sub-micron technologies, process variations can cause significant path delay and clock skew uncertainties thereby lead to timing failure and yield loss. In this paper, we propose a comprehensive clock scheduling methodology that improves timing and yield through both pre-silicon clock scheduling and post-silicon clock tuning. First, an optimal clock scheduling algorithm has been developed to allocate the slack for each path according to its timing uncertainty. To balance the skew that can be caused by process variations, programmable delay elements are inserted at the clock inputs of a small set of flip-flops on the timing critical paths. A delay-fault testing scheme combined with linear programming is used to identify and eliminate timing violations in the manufactured chips. Experimental results show that our methodology achieves substantial yield improvement over a traditional clock scheduling algorithm in many of the ISCAS89 benchmark circuits, and obtain an average yield improvement of 13.6%.

Random access scan: a solution to test power, test data volume and test time

Adherence to serial scan is preventing the researchers from investigating alternative design for test techniques that may offer larger test benefit at the cost of some what higher overhead. In this paper, we investigate the use of random access scan for simultaneous reduction of test power, test data volume and test application time. We provide an asymmetric traveling salesman formulation of these problems to minimize random access scans and the test data. Application of our method results into nearly 3/spl times/ speedup in test application time, 60% reduction in test data volume and over 99% reduction in power consumption for benchmark circuits.

Exclusive test and its applications to fault diagnosis

We introduce a new type of test, called exclusive test, and discuss its application to fault diagnosis in combinational circuits. A test that detects exactly one fault from a given pair of faults is called an exclusive test. In general, generation of an exclusive test by a conventional automatic test generator requires a model of the circuit with multiple-faults. We describe an ATPG model that transforms the exclusive test problem into a single-fault test generation problem. We present a generalized diagnostic method and illustrate the use of exclusive tests in improving the diagnostic resolution of a test set. Results of diagnosis with exclusive tests for ISCAS85 benchmark circuits are included.

Progressive random access scan: a simultaneous solution to test power, test data volume and test time

Traditional testing research for testing VLSI circuits has been confined to the use of serial scan test architecture whose origin lies in keeping the hardware overhead low. However, there has been a paradigm shift in the cost factor - the transistor cost has been dropping exponentially whereas the test cost is starting to increase. We believe that adding marginally more hardware is acceptable provided the test cost can be reduced considerably. This paper takes such a view of testing and rejuvenates the random access scan as a design for testability method that simultaneously addresses three limitations of the traditional serial scan namely, test data volume, test application time, and test power. The novelty of the progressive random access scan approach proposed in this paper lies in developing the test architecture and formulating the test application time and test data volume reduction problems. We provide a traveling salesman formulation of these problems in our test architecture setting. Experimental results show the practicality of our approach as the hardware cost components, consisting of routing and transistor count, increase only marginally compared to the serial scan approach whereas there is a dramatic decrease in test power consumption (nearly a 1000 fold decrease in average test power) as well as the test data volume and the test times are halved

Yield-driven, false-path-aware clock skew scheduling

Semiconductor technology advances have enabled designers to integrate more functionality in a single chip. As design complexity increases, many new design techniques are developed to optimize chip area and power consumption, as well as performance. Traditionally, yield improvement has been achieved through process improvement. However, in deep-submicron technologies, process variations are difficult to control. As a result, many design decisions significantly affect yield. Therefore, designers should consider yield-related issues during the design phase. This article proposes clock skew scheduling as a tool to address causes of performance-related circuit yield loss. It is an interesting example of how managing circuit-level parameters can have a direct impact on yield metrics and therefore a clear example of the direction of DFM research.

Test cost reduction using partitioned grid random access scan

The random access scan (RAS) has the ability to address major problems associated with serial-scan method. A practically implementable RAS test architecture called progressive random access scan (PRAS) was introduced earlier. This paper proposes a generalized architecture for the PRAS. We show that the generalized PRAS architecture offers two orders of magnitude gains in test application time over traditional serial scan and is superior to multiple serial scan in terms of the use of tester channels.

State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data Size

Three issues that are dominating test research today are test application time, test data volume and test power. Researchers have focused on these issues mostly considering the popular serial scan architecture for its relatively low hardware overhead while ignoring the fact that exponential drop in hardware cost offers opportunities for implementing a test architecture that previously may have been unacceptable. This paper takes such a paradigm shift into account and studies the simultaneous solution of all three problems of serial scan by making use of progressive random access scan test architecture. This architecture only increases the hardware cost marginally while providing marked improvements for the three issues. This paper explains the test architecture and then develops a test generation methodology which reduces the test application time by nearly 75%, test data volume by 50% for the benchmark circuits. Above all, the architecture is inherently so efficient that it reduces the test power by nearly 99% or more of the test power consumption compared to serial scan

Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan

Studies of random-access scan (RAS) architecture have largely limited their scope to reduce test application time, test volume and test power to detect conventional stuck-at faults. This paper proposed an enhanced RAS latch design for two pattern tests. The proposed latch is a minor modification of the RAS latch and is well suited for delay-fault tests. In contrast, the traditional serial scan latch needs a major enhancement. As a result the RAS may offer a hardware advantage while the test time is nearly halved over the serial scan design. The test time advantage in this paper was demonstrated for various test sets for benchmark circuits and the authors argued that the advantage is even larger when test sets are generated for RAS architecture in mind, as well as by the exploitation of unspecified bits in test vectors

False path and clock scheduling based yield-aware gate sizing

Timing margin (slack) needs to be carefully managed to ensure a satisfactory timing yield. We propose a new design flow that combines a false-path-aware gate sizing and a statistical-timing-driven clock scheduling algorithms to maximize timing yield. Our gate sizing algorithm preserves the true path lengths that may otherwise be altered by the traditional gate sizing algorithms due to the presence of false paths. The slack is then distributed to each path according to its path delay uncertainty to maximize the timing yield. Experimental results show that our flow achieves significant timing yield improvements (> 20%) than a traditional flow for a subset of the benchmark circuits with little or negligible area penalty.