Seiji Kajihara

On test data volume reduction for multiple scan chain designs

We consider issues related to the reduction of scan test data in designs with multiple scan chains. We propose a metric that can be used to evaluate the effectiveness of procedures for reducing the scan data volume. The metric compares the achieved compression to the compression which is intrinsic to the use of multiple scan chains. We also propose a procedure for modifying a given test set so as to achieve reductions in test data volume assuming a combinational decompressor circuit.

XID: Don't care identification of test patterns for combinational circuits

Given a test set for stuck-at faults of a combinational circuit or a full-scan sequential circuit, some of the primary input values may be changed to the opposite logic values without losing fault coverage. We can regard such input values as dont care (X). In this paper, we propose a method for identifying the X inputs of test vectors in a given test set. While there are many combinations of X inputs in the test set generally, the proposed method finds one including as many X inputs as possible, by using fault simulation and procedures similar to implication and justification of automatic test pattern generation (ATPG) algorithms. Experimental results for ISCAS benchmark circuits show that approximately 69% of the inputs of uncompacted test sets could be X on the average. Even for highly compacted test sets, the method found that approximately 48% of inputs are X.

On selecting testable paths in scan designs

We propose an efficient method to select a minimal set of testable paths in scan designs, such that every line in the circuit is covered by at least one of the longest testable paths that contain it (if there are any). The proposed path selection approach is based on a stepwise path expansion procedure that uses delay information and compact information about untestable paths to select longest paths while avoiding untestable paths. Techniques called delay analysis and delay-constrained path expansion are used to speedup the selection of paths to test. Compared to earlier approaches, the proposed approach is fast and it is guaranteed to find testable paths. Additionally the procedure also derives tests for the selected paths. Experimental results for ISCAS89 benchmark circuits using standard scan and broadside testing are presented to demonstrate the effectiveness of the proposed method.

A Framework of High-quality Transition Fault ATPG for Scan Circuits

This paper presents a framework of high-quality test generation for transition faults in full scan circuits. This work assumes a restricted broad-side testing as a test application method for two-pattern tests where control of primary inputs and observation of primary outputs are restricted. Because we use a modified time expansion model of a circuit-under-test during ATPG and fault simulation, conventional ATPG and fault simulation programs can work with minor change. The proposed ATPG method consists of two algorithms, which are activation-first and propagation-first, and for each fault it is decided which algorithm should be applied. Test patterns are generated such that transition faults with small delay can be detected, i.e. a path for fault excitation and propagation becomes as long as possible. In experimental results we evaluate test patterns generated by the proposed method using SDQM that calculates delay test quality, and show the effectiveness of the proposed method

On per-test fault diagnosis using the X-fault model

This work proposes a new per-test fault diagnosis method based on the X-fault model. The X-fault model represents all possible behaviors of a physical defect or defects in a gate and/or on its fanout branches by using different X symbols on the fanout branches. A novel technique is proposed for analyzing the relation between observed and simulated responses to extract diagnostic information and to score the results of diagnosis. Experimental results show the effectiveness of our method.

Multiple scan tree design with test vector modification

In this paper, we propose a method of test compression for multiple scan designs. Instead of the conventional serial scan chains, the proposed method constructs scan trees in which scan flip-flops are placed and routed in a tree structure. Inputs of the scan trees drive several scan trees of different lengths (height). Since test data volume and test application time are dominated by the scan tree with the maximum height among the constructed scan trees, the proposed method distributes the scan flip-flops to the scan trees so as to minimize the maximum height of the scan trees. In addition, the proposed method modifies the given test vectors to maximize the reduction in test application time. Experimental results for ISCAS-89 benchmark circuits show that the proposed method could reduce, on the average, test data volume by 77% compared with the conventional multiple scan design. The scan tree construction enlarges the number of scan outputs required. However test data volume could be reduced by 66% even if the number of scan outputs is limited.

Efficient space/time compression to reduce test data volume and testing time for IP cores

We present 2D (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) cores. We start with a set of test cubes and use the well-known concept of scan chain compatibility to determine a small number c of tester channels that are needed to drive m scan chains (c /spl Lt/ m). Next, we exploit logic dependencies between the test data for the scan chains to design a single-level decompression circuit based on two-input gates. We refer to these procedures collectively as width (space) compression. We then determine a small set of test patterns that can provide complete fault coverage when they are applied to the circuit under test using the c tester channels; this procedure is referred to as height (time) compression. In this way, structural information about the IP cores is not necessary for fault simulation, dynamic compaction, or test generation. The hardware overhead of the proposed approach is limited to the fan-out structure and a very small number of gates between the tester-driven external scan pins and the internal scan chains. Results are presented for the ISCAS-89 benchmarks and for four industrial circuits.

Test data compression using don't-care identification and statistical encoding

This paper describes a method of test data compression for a given test set using statistical encoding. In order to maximize the effectiveness of statistical encoding, the method first converts some specified values of test vectors to unspecified ones without losing fault coverage, and then reassigns appropriate logic values to the unspecified inputs. Experimental results for ISCAS-89 benchmark circuits show that the proposed method could reduce test data volume to less than 40% of the original test sets.

Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values

When test vectors for a full scan logic circuit include unspecified values, conventional 3-valued fault simulation may not compute the exact fault coverage for single stuck-at faults. This paper first addresses the incompleteness of logic/fault simulation based on the conventional 3-valued logic. Then we propose an enhanced method of logic/fault simulation to compute more accurate fault coverage using implicit logic values. The proposed method employs indirect implications. We also propose a new learning criterion to identify indirect implications that are not identified by earlier static learning procedure. Since some indirect implications derived from a fault-free circuit become invalid in the presence of a fault, we use a sufficient condition for an indirect implication to remain valid for the faulty circuit, and give an efficient procedure for more accurate fault simulation. Experimental results demonstrate that the proposed method reduces the number of unknown values at the circuit outputs in logic simulation, and hence it discovers several detected faults that are not declared as detected by the conventional fault simulation.

A method of static test compaction based on don't care identification

In this paper, we propose a procedure to compact a test set for a combinational circuit. Given a test set in which all input values are specified, the procedure first identifies dont care inputs of the test set, and next reassigns appropriate values to the dont cares to achieve test compaction. The procedure can be applied repeatedly, until further compaction cannot be derived. Experimental results show effectiveness of the proposed procedure for the ISCAS benchmark circuits.