Dong Ji

Normally OFF Trench CAVET With Active Mg-Doped GaN as Current Blocking Layer

A normally OFF trench current aperture vertical electron transistor (CAVET) was designed and successfully fabricated with Mg-doped p-GaN current blocking layers. The buried Mg-doped GaN was activated using a postregrowth annealing process. The source-to-drain body diode showed an excellent p-n junction characteristics, blocking over 1 kV, sustaining a maximum blocking electric field of 3.8 MV/cm. Three-terminal breakdown voltages of trench-CAVETs, measured up to 225 V, were limited by dielectric breakdown. This paper highlights the achievement of the well-behaved buried p-n junction that has been a formidable challenge in the success of vertical GaN devices.

Design of 1.2 kV Power Switches With Low

Two novel gallium nitride-based vertical junction FETs (VJFETs), one with a vertical channel and the other with a lateral channel, are proposed, designed, and modeled to achieve a 1.2 kV normally OFF power switch with very low ON resistance (R_ON). The 2-D drift diffusion model of the proposed devices was implemented using Silvaco ATLAS. A comprehensive design space was generated for the vertical channel VJFET (VC-VJFET). For a well-designed VC-VJFET, the breakdown voltage (V_BR) obtained was 1260 V, which is defined in this study as the drain-to-source voltage at an OFF-state current of 1 μA · cm^-2 and a peak electric field not exceeding 2.4 MV/cm. The corresponding R_ON was 5.2 mΩ · cm². To further improve the switching device figure of merit, a merged lateral-vertical geometry was proposed and modeled in the form of a lateral channel VJFET (LC-VJFET). For the LC-VJFET, a breakdown voltage of 1310 V with a corresponding R_ON of 1.7 mQ · cm² was achieved for similar thicknesses of the drift region. This paper studies the design space in detail and discusses the associated tradeoffs in the R_ON and V_BR in conjunction with the threshold voltage (V_T) desired for the normally OFF operation.

R_{\mathrm{{\scriptscriptstyle ON}}}

The focus of this paper is to understand the impact of the material properties of GaN, exploited using a vertical device, in power switching by estimating switching loss. The study was performed with a cascoded current aperture vertical electron transistor (CAVET). The normally OFF device was simulated and analyzed using a Silvaco ATLAS 2-D drift diffusion model integrated to SPICE-based circuit simulator. Besides evaluating the performance space and, hence, potential application space for GaN CAVETs, this paper presents significant accomplishment in establishing a device to circuit model, thereby, offering a reliable method of evaluating GaN-based power transistors. The accuracy of the model was established through the excellent agreement of simulated data with the data sheet specs of a commercial cascoded GaN high electron mobility transistor. The model was successfully applied to compare SiC MOSFETs with GaN CAVETs. A cascoded GaN CAVET has

Using GaN-Based Vertical JFET

2\times

Dynamic Modeling and Power Loss Analysis of High-Frequency Power Switches Based on GaN CAVET

faster switching time,

Dispersion Free 450-V p GaN-Gated CAVETs With Mg-ion Implanted Blocking Layer

3\times

First report of scaling a normally-off in-situ oxide, GaN interlayer based vertical trench MOSFET (OG-FET)

lower switching loss compared with standard commercial SiC MOSFET, owing to the higher electron mobility in GaN. Operating at frequencies of megahertz with low power loss, a GaN CAVET will, therefore, lead to smaller converter size and higher system efficiency.

Vertical GaN Transistors for Power Electronics

In this letter, a GaN-based current aperture vertical electron transistor (CAVET) with a p-type gate layer and an implantation-based current blocking structure is presented. The devices measured showed a breakdown voltage of 450 V and no dispersion. The factors limiting higher breakdown voltages in these devices were carefully studied and discussed. The devices were grown on sapphire and relied on a box-shaped Mg implanted current blocking scheme. This is the first demonstration of an implantation-based CAVET, grown on sapphire blocking of 450 V with respectable on-state characteristics.

Impact of Trench Dimensions on the Device Performance of GaN Vertical Trench MOSFETs

GaN lateral transistors (HEMTs) continue to penetrate the power electronics market demonstrating excellent performance in the medium power applications. However, for power applications 10kW and higher, vertical GaN devices are preferred over lateral one, since the former offers higher current and power densities. To date, several different vertical transistor structures have been proposed and reported, such as in-situ oxide based vertical trench MOSFET with an undoped GaN interlayer as a channel (OGFET) [1, 2], current aperture vertical electron transistors (CAVETs) [3, 4], junction field effect transistors (JFETs) [5, 6] and MOSFETs [7, 8]. Gupta et al. have demonstrated the high performance OGFET with low specific on-state resistance (Ron, sp) recently [1]. This study presents the large device scaling of the OGFET to realize high output current.

Switching performance analysis of GaN OG-FET using TCAD device-circuit-integrated model

The chapter titled “Vertical GaN Transistors for Power Electronics” takes the reader through the research and development cycle of GaN vertical-device technology, detailing out the three-terminal devices developed over the last decade. Power converters rely on solid state devices featuring diodes and transistors as their basic building blocks. GaN technology is an ever-expanding topic for R&D, proving its potential to solve several challenges in power conversion that cannot be addressed by Si. Medium-voltage (650–900 V) devices using the HEMT configuration have been able to reduce form factor at the system level by driving circuits at higher frequencies (100KHz–1 MHz) and eliminating heat sinks or reducing cooling requirements. Such potentials sparked the interest in GaN device research to address power conversion needs. However, in power conversion the demand of high current (50A and higher) from a single chip for a rated voltage (1KV and higher) is a standard requirement. Particularly when the market is favorable toward electrification of cars and other means of transportations, GaN must expand its scope to provide high power solutions with higher power density compared to Si and even SiC. Vertical devices have been the choice of power device engineers for economic use of the material and maximum use of its physical properties (which allow highest possible blocking field, field mobility, etc.). In this chapter, we discuss vertical transistors first in its normally on form (CAVETs) and then in its normally off design (MOSFET). The advantages and disadvantages are discussed for each type besides describing their operation principles. We have tried to make this chapter scholastic and informative by use of modeling and experimental data for each device we describe. The chapter will help the reader to realize the most recent status of GaN vertical transistors and appreciate its potential in power conversion.