Chirag Gupta

OG-FET: An In-Situ

In this letter, a novel device design to achieve both low ON-resistance and enhancement mode operation in a vertical GaN FET is demonstrated. In the traditional trench MOSFET structure, a dielectric is deposited on an n-p-n trenched structure and the channel forms via p-GaN inversion at the dielectric/p-GaN interface. However, this results in a relatively high ON-resistance due to poor electron mobility in the channel. By changing the structure to include a metal-organic chemical vapor deposition (MOCVD)-regrown Un-intentionally Doped (UID)-GaN interlayer followed by an in-situ dielectric (MOCVD Al2O3) cap on the n-p-n trenched structure, a pathway (channel) for enhanced electron mobility is created, resulting in reduced ON-resistance. Preliminary results for this device design demonstrated almost 60% reduction in the ON-resistance and similar breakdown voltage compared with a traditional trench MOSFET structure while maintaining normally off operation with a threshold voltage of 2 V.

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GaN is one of the best suited materials for high-power devices due to its superior material properties such as high breakdown field, wide band gap and high saturation drift velocity. Consequently, GaN power devices have gained increased attention in recent years. Numerous vertical GaN power transistors have been demonstrated in the past few years [1-4]. One of the preferred GaN vertical device designs is the trench MOSFET. In the traditional trench MOSFET structure [2-4], the channel forms via p-GaN inversion at the dielectric/p-GaN interface resulting in a relatively high on-resistance due to the poor electron mobility in the channel. In this work, we present a novel device design to lower the on-resistance in a trench MOSFET. By inserting a MOCVD regrown GaN interlayer prior to the dielectric deposition (MOCVD Al2O3) on the trenched structure, lower on-resistance is achieved due to enhancement in the electron mobility of the channel. For an optimal GaN interlayer thickness of 10 nm, a low on-resistance (active area) of 0.97 mΩ.cm2 alongside enhancement mode operation (Vth = 3 V) is demonstrated.

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In this paper, we report on the growth and electrical characterization of (Al,Si)O dielectrics grown by metalorganic chemical vapor deposition (MOCVD) using trimethylaluminum, oxygen, and silane as precursors. The growth rates, refractive indices, and composition of (Al,Si)O films grown on Si(001) were determined from ellipsometry and XPS measurements. Crystallinity and electrical properties of (Al,Si)O films grown in situ on c-plane GaN were characterized using grazing incidence X-ray diffraction and capacitance–voltage with current–voltage measurements, respectively. Si concentration in the films was found to be tunable by varying the trimethylaluminum and/or oxygen precursor flows. The Si incorporation suppressed the formation of crystalline domains, leading to amorphous films that resulted in reduced interfacial trap density, low gate leakage and ultra-low hysteresis in (Al,Si)O/n-GaN MOS-capacitors.

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GaN trench-gate MOSFETs with m- and a-plane-oriented sidewall channels were fabricated and characterized. The trench-gate MOSFET performance depended strongly on the sidewall-MOS-channel plane orientation. The m-plane-oriented MOS channel devices demonstrated higher channel mobility, higher current density, lower sub-threshold slope, and lower hysteresis with similar threshold voltage and on–off ratio compared to a-plane MOS channel devices. These results indicate that orienting trench-gate MOSFET toward the m-plane would allow for better on-state characteristics while maintaining similar off-state characteristics.

aN Interlayer-Based Vertical Trench MOSFET

In recent years, GaN trench MOSFETs have been actively investigated to achieve low on-resistance and high breakdown voltage [1-8]. The absence of a JFET region makes the trench MOSFET a favorable device structure to reduce the on-resistance. However, poor (electron) channel mobility in GaN trench MOSFETs lead to increased channel resistance. This could potentially result in reliability issues and/or high on-resistance as a large gate bias is needed to reduce the channel resistance. In our previous works, we demonstrated a novel device design (OG-FET), where enhanced channel mobility was obtained by inserting a MOCVD-regrown GaN interlayer between the trenched structure and the in-situ gate dielectric [7, 8]. The breakdown performance of OG-FETs reported in previous work was limited due to the absence of edge termination [8]. In this work, OG-FETs were fabricated with field plate based edge termination which resulted in an enhanced breakdown from 600 V (EBR ∼ 1.5 MV/cm) to 1000 V (EBR ∼ 2 MV/cm).

A novel device design to lower the on-resistance in GaN trench MOSFETs

GaN lateral transistors (HEMTs) continue to penetrate the power electronics market demonstrating excellent performance in the medium power applications. However, for power applications 10kW and higher, vertical GaN devices are preferred over lateral one, since the former offers higher current and power densities. To date, several different vertical transistor structures have been proposed and reported, such as in-situ oxide based vertical trench MOSFET with an undoped GaN interlayer as a channel (OGFET) [1, 2], current aperture vertical electron transistors (CAVETs) [3, 4], junction field effect transistors (JFETs) [5, 6] and MOSFETs [7, 8]. Gupta et al. have demonstrated the high performance OGFET with low specific on-state resistance (Ron, sp) recently [1]. This study presents the large device scaling of the OGFET to realize high output current.

Metalorganic chemical vapor deposition and characterization of (Al,Si)O dielectrics for GaN-based devices

Controlled n-type doping down to 2 × 1015 cm−3 was achieved in GaN grown on sapphire by MOCVD by balancing the n-type Si doping with respect to the background carbon and oxygen levels. A dopant level of ~1 × 1016 cm−3 displayed a very high mobility of 899 cm2 V−1 s−1. High electron mobility in the drift layer leads to a low on resistance and high current densities without compromising on any other properties of the device. Schottky diodes processed on these low n-type layers showed low R on values, while the p–n diodes display high reverse breakdown voltages in excess of 1000 V for 8 μm thick drift layers with a doping of 2 × 1015 cm−3.

Comparing electrical performance of GaN trench-gate MOSFETs with a-plane and m-plane sidewall channels

In this letter, we have examined the impact of trench dimensions on the breakdown voltage and ON-resistance of trench MOSFETs fabricated on sapphire and bulk GaN substrates. Contrary to simulation studies, the breakdown voltage decreased with an increase in trench dimensions in devices fabricated on sapphire substrates. However, such breakdown voltage dependence with trench dimensions was not observed in devices fabricated on bulk GaN substrates of the same area. The observed trend on GaN on sapphire devices was associated with the equivalently reduced number of dislocations per device area. These results give an insight into how dislocations could affect breakdown voltage in power MOSFETs.

1 kV field plated in-situ oxide, GaN interlayer based vertical trench MOSFET (OG-FET)

Blanket regrowth studies were performed on GaN trenches with varying widths and optimized for two types of devices—those that required the profile of the trench to be maintained and those that required the complete filling of trenches, i.e., a planar surface after regrowth. Low temperature Al0.22Ga0.78N growth was optimized and used as the marker layer for SEM. GaN deposition at a medium temperature of 950 °C and using N2 as carrier gas resulted primarily in growth on the (0001) plane, while the growth on the sidewalls was governed by the formation of slow growing semi-polar planes. This gave a conformal profile to the regrown GaN—useful for regrown GaN interlayer based vertical trench MOSFETs. In contrast, high temperature (1150 °C) growth in H2 resulted in high lateral growth rates. The planar surface was achieved under these conditions—a very promising result for CAVET-type devices.

First report of scaling a normally-off in-situ oxide, GaN interlayer based vertical trench MOSFET (OG-FET)

A polarization-induced three-dimensional hole gas (3DHG) was demonstrated in undoped and compositionally graded In x Ga1− x N layers. All samples were grown on Ga-face bulk GaN substrates by metal organic chemical vapor deposition. A high hole concentration of 2.8 × 1018 cm−3 was obtained in a 100-nm-thick In x Ga1− x N layer where the indium composition was graded from x = 0 to x = 0.2. 3DHG density control by varying the indium composition and thickness of a compositionally graded In x Ga1− x N layer was also demonstrated.