Anchal Agarwal

Normally OFF Trench CAVET With Active Mg-Doped GaN as Current Blocking Layer

A normally OFF trench current aperture vertical electron transistor (CAVET) was designed and successfully fabricated with Mg-doped p-GaN current blocking layers. The buried Mg-doped GaN was activated using a postregrowth annealing process. The source-to-drain body diode showed an excellent p-n junction characteristics, blocking over 1 kV, sustaining a maximum blocking electric field of 3.8 MV/cm. Three-terminal breakdown voltages of trench-CAVETs, measured up to 225 V, were limited by dielectric breakdown. This paper highlights the achievement of the well-behaved buried p-n junction that has been a formidable challenge in the success of vertical GaN devices.

OG-FET: An In-Situ

In this letter, a novel device design to achieve both low ON-resistance and enhancement mode operation in a vertical GaN FET is demonstrated. In the traditional trench MOSFET structure, a dielectric is deposited on an n-p-n trenched structure and the channel forms via p-GaN inversion at the dielectric/p-GaN interface. However, this results in a relatively high ON-resistance due to poor electron mobility in the channel. By changing the structure to include a metal-organic chemical vapor deposition (MOCVD)-regrown Un-intentionally Doped (UID)-GaN interlayer followed by an in-situ dielectric (MOCVD Al2O3) cap on the n-p-n trenched structure, a pathway (channel) for enhanced electron mobility is created, resulting in reduced ON-resistance. Preliminary results for this device design demonstrated almost 60% reduction in the ON-resistance and similar breakdown voltage compared with a traditional trench MOSFET structure while maintaining normally off operation with a threshold voltage of 2 V.

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GaN is one of the best suited materials for high-power devices due to its superior material properties such as high breakdown field, wide band gap and high saturation drift velocity. Consequently, GaN power devices have gained increased attention in recent years. Numerous vertical GaN power transistors have been demonstrated in the past few years [1-4]. One of the preferred GaN vertical device designs is the trench MOSFET. In the traditional trench MOSFET structure [2-4], the channel forms via p-GaN inversion at the dielectric/p-GaN interface resulting in a relatively high on-resistance due to the poor electron mobility in the channel. In this work, we present a novel device design to lower the on-resistance in a trench MOSFET. By inserting a MOCVD regrown GaN interlayer prior to the dielectric deposition (MOCVD Al2O3) on the trenched structure, lower on-resistance is achieved due to enhancement in the electron mobility of the channel. For an optimal GaN interlayer thickness of 10 nm, a low on-resistance (active area) of 0.97 mΩ.cm2 alongside enhancement mode operation (Vth = 3 V) is demonstrated.

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GaN trench-gate MOSFETs with m- and a-plane-oriented sidewall channels were fabricated and characterized. The trench-gate MOSFET performance depended strongly on the sidewall-MOS-channel plane orientation. The m-plane-oriented MOS channel devices demonstrated higher channel mobility, higher current density, lower sub-threshold slope, and lower hysteresis with similar threshold voltage and on–off ratio compared to a-plane MOS channel devices. These results indicate that orienting trench-gate MOSFET toward the m-plane would allow for better on-state characteristics while maintaining similar off-state characteristics.

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In recent years, GaN trench MOSFETs have been actively investigated to achieve low on-resistance and high breakdown voltage [1-8]. The absence of a JFET region makes the trench MOSFET a favorable device structure to reduce the on-resistance. However, poor (electron) channel mobility in GaN trench MOSFETs lead to increased channel resistance. This could potentially result in reliability issues and/or high on-resistance as a large gate bias is needed to reduce the channel resistance. In our previous works, we demonstrated a novel device design (OG-FET), where enhanced channel mobility was obtained by inserting a MOCVD-regrown GaN interlayer between the trenched structure and the in-situ gate dielectric [7, 8]. The breakdown performance of OG-FETs reported in previous work was limited due to the absence of edge termination [8]. In this work, OG-FETs were fabricated with field plate based edge termination which resulted in an enhanced breakdown from 600 V (EBR ∼ 1.5 MV/cm) to 1000 V (EBR ∼ 2 MV/cm).

aN Interlayer-Based Vertical Trench MOSFET

Low temperature (LT) flow modulation epitaxy (FME) or “pulsed” growth was successfully used to prevent magnesium from Metalorganic Chemical Vapor Deposition (MOCVD) grown p-GaN:Mg layers riding into subsequently deposited n-type layers. Mg concentration in the subsequent layers was lowered from ∼1 × 1018 cm−3 for a medium temperature growth at 950 °C to ∼1 × 1016 cm−3 for a low temperature growth at 700 °C via FME. The slope of the Mg concentration drop in the 700 °C FME sample was 20 nm/dec—the lowest ever demonstrated by MOCVD. For growth on Mg implanted GaN layers, the drop for a medium temperature regrowth at 950 °C was ∼10 nm/dec compared to >120 nm/dec for a high temperature regrowth at 1150 °C. This drop-rate obtained at 950 °C or lower was maintained even when the growth temperature in the following layers was raised to 1150 °C. A controlled silicon doping series using LT FME was also demonstrated with the lowest and highest achieved doping levels being 5 × 1016 cm−3 and 6 × 1019 cm−3, respectively.

A novel device design to lower the on-resistance in GaN trench MOSFETs

In this letter, a GaN-based current aperture vertical electron transistor (CAVET) with a p-type gate layer and an implantation-based current blocking structure is presented. The devices measured showed a breakdown voltage of 450 V and no dispersion. The factors limiting higher breakdown voltages in these devices were carefully studied and discussed. The devices were grown on sapphire and relied on a box-shaped Mg implanted current blocking scheme. This is the first demonstration of an implantation-based CAVET, grown on sapphire blocking of 450 V with respectable on-state characteristics.

Comparing electrical performance of GaN trench-gate MOSFETs with a-plane and m-plane sidewall channels

GaN lateral transistors (HEMTs) continue to penetrate the power electronics market demonstrating excellent performance in the medium power applications. However, for power applications 10kW and higher, vertical GaN devices are preferred over lateral one, since the former offers higher current and power densities. To date, several different vertical transistor structures have been proposed and reported, such as in-situ oxide based vertical trench MOSFET with an undoped GaN interlayer as a channel (OGFET) [1, 2], current aperture vertical electron transistors (CAVETs) [3, 4], junction field effect transistors (JFETs) [5, 6] and MOSFETs [7, 8]. Gupta et al. have demonstrated the high performance OGFET with low specific on-state resistance (Ron, sp) recently [1]. This study presents the large device scaling of the OGFET to realize high output current.

1 kV field plated in-situ oxide, GaN interlayer based vertical trench MOSFET (OG-FET)

Controlled n-type doping down to 2 × 1015 cm−3 was achieved in GaN grown on sapphire by MOCVD by balancing the n-type Si doping with respect to the background carbon and oxygen levels. A dopant level of ~1 × 1016 cm−3 displayed a very high mobility of 899 cm2 V−1 s−1. High electron mobility in the drift layer leads to a low on resistance and high current densities without compromising on any other properties of the device. Schottky diodes processed on these low n-type layers showed low R on values, while the p–n diodes display high reverse breakdown voltages in excess of 1000 V for 8 μm thick drift layers with a doping of 2 × 1015 cm−3.

Suppression of Mg propagation into subsequent layers grown by MOCVD

In this work, a study of two different types of current aperture vertical electron transistor (CAVET) with ion-implanted blocking layer are presented. The device fabrication and performance limitation of a CAVET with a dielectric gate is discussed, and the breakdown limiting structure is evaluated using on-wafer test structures. The gate dielectric limited the device breakdown to 50V, while the blocking layer was able to withstand over 400V. To improve the device performance, an alternative CAVET structure with a p-GaN gate instead of dielectric is designed and realized. The pGaN gated CAVET structure increased the breakdown voltage to over 400V. Measurement of test structures on the wafer showed the breakdown was limited by the blocking layer instead of the gate p-n junction.