Dong Sam Ha

HOPE: an efficient parallel fault simulator for synchronous sequential circuits

HOPE is an efficient parallel fault simulator for synchronous sequential circuits that employs the parallel version of the single fault propagation technique. HOPE is based on an earlier fault simulator railed PROOFS, which employs several heuristics to efficiently drop faults and to avoid simulation of many inactive faults. In this paper, we propose three new techniques that substantially speed up parallel fault simulation: (1) reduction of faults simulated in parallel through mapping nonstem faults to stem faults, (2) a new fault injection method called functional fault injection, and (3) a combination of a static fault ordering method and a dynamic fault ordering method. Based on our experiments, our fault simulator, HOPE, which incorporates the proposed techniques, is about 1.6 times faster than PROOFS for 16 benchmark circuits.

On using signature registers as pseudorandom pattern generators in built-in self-testing

Signature registers are commonly used to collect test responses in built-in self-testing (BIST). If the contents of signature registers can be used as test patterns, the overall testing time can be reduced due to improved testing parallelism. Moreover, the number of extra registers for implementing BIST could be reduced. Here, the characteristics of the patterns generated by signature registers are studied through analyses as well as experiments. It is shown that the patterns generated by signature registers are rarely repeated when the number of test patterns is relatively small compared to the number of possible patterns. It is also shown that the patterns generated are almost uniformly distributed. Therefore, signature registers can be used effectively as pseudorandom pattern generators. The practicality of using signature registers as pseudorandom pattern generators is investigated by fault simulation experiments using an example circuit. >

SOPRANO: an efficient automatic test pattern generator for stuck-open faults in CMOS combinational circuits

In this paper, we describe a highly efficient automatic test pattern generator for stuck-open (SOP) faults, called SOPRANO, in CMOS combinational circuits. The key idea of SOPRANO is to convert a CMOS circuit into an equivalent gate level circuit and SOP faults into the equivalent stuck-at faults. Then SOPRANO derives test patterns for SOP faults using a gate level test pattern generator. Several techniques to reduce the test set size are introduced in SOPRANO. Experimental results performed on eight benchmark circuits show that SOPRANO achieves high SOP fault coverage and short processing time.

New methods of improving parallel fault simulation in synchronous sequential circuits

A highly successful parallel fault simulator, called PROOFS, for synchronous sequential circuits has been reported. The performance of PROOFS has been substantially improved in HOPE. In HOPE, a systematic way of screening out faults with short propagation zone is proposed. We propose several new techniques which further reduce the fault simulation time of HOPE. The new techniques are: functional fault injection, static fault ordering by fanout free regions and dynamic fault ordering of potentially detected faults. The three methods are incorporated into HOPE and called HOPE1.1. HOPE1.1 shows significant improvement in performance for all the benchmark circuits experimented as compared to HOPE. Experimental results show that HOPE1.1 is especially effective for large circuits. For s35932 which is the largest circuit experimented with, the number of events is reduced by 24%, and the CPU time by 53% compared to HOPE.

Automatic insertion of BIST hardware using VHDL

A system is presented which automatically inserts BIST (built-in self-testing) hardware to a circuit described in VHDL (VHSIC Hardware Description Language). An appropriate VHDL modeling style for automatic insertion of BIST hardware is investigated. The use of BILBO (built-in logic block observer) is primarily pursued in the system. Algorithmic and rule-based approaches are used in the insertion of BILBO. Test scheduling and control signal distribution are also performed by the system.<<ETX>>

Test Pattern Generation for Stuck-Open Faults Using Stuck-At Test Sets in CMOS Combinational Circuits

In this paper we investigate two aspects regarding the detection of stuck-open (SOP) faults using stuck-at test sets. First, we measure the SOP fault coverage of stuck-at test sets for various CMOS combinational circuits. The SOP fault coverage is compared with that of random pattern test sets. Second, we propose a method to improve the SOP fault coverage of stuck-at test sets by organizing the test sequence of stuck-at test sets. The performance of the proposed method is compared with that of a competing method. Experimental results show that the proposed method leads to smaller test sets and shorter processing time while achieving high SOP fault coverage.

BIDES: a BIST design expert system

BIDES is an expert system for incorporating BIST into a hardware design that is described in VHDL. Based on the BILBO technique, the BIDES system allocates pseudorandom pattern generators and signature analysis registers to each combinational logic module in a design in such a way that given constraints on testing time and hardware overhead are satisfied. This assignment is performed using the iterative process of regeneration and evaluation of various BIST implementations. In order to effectively perform regeneration, an abstraction hierarchy for a BIST design is introduced and a hierarchical planning technique is employed using this structure. This formulation also leads to an easily modifiable system. Prolog is used for implementing the system.

On the design of random pattern testable PLA based on weighted random pattern testing

Programmable Logic Arrays (PLAs) provide a cost effective method to realize combinational logic circuits. PLAs are often not suitable for random pattern testing due to high fao-in of gates. In order to reduce the effective fan-in of gates, previous random pattern testable (RPT) PLA designs focused on partitioning inputs and product lines. In this paper we propose a new random pattern testable design of PLAs which is suitable for built-in selftest. The key idea of the proposed design is to apply weighted random patterns to the PLA under test. The proposed design method was applied to 30 example PLAs. The performance of the RPT PLAs was measured in the size of test set, area overhead, and time overhead, and compared with two other designs in test length and fault coverage. The experimental results show that the proposed design achieve short test length and high fault coverage.

On the design of pseudoexhaustive testable PLAs

A method is presented to design pseudoexhaustive testable (PET) PLAs (programmable logic arrays) that are suitable for BIST (built-in self-test) environments. The key idea of the design is to partition inputs and product lines into groups. During testing, a group of inputs and a group of product lines are selected and tested exhaustively. The proposed design leads to small test sizes and relatively small area overhead. Experimental results on 30 PLAs, comparing test set sizes and area overhead of different BIST PLA designs, are reported. >

Comments on "A method of fault simulation based on stem regions

For the original article see ibid., vol.9, no.2, p.212-20 (1990). The commenters show a counterexample for the region extraction algorithm given in the above-mentioned work by F. Maamari and J. Rajski. A four-step region extraction algorithm was given to extract the exit lines of each stem. In steps 1 and 2, primary reconvergent gates (PRGs) and secondary reconvergent gates (SRGs) of the stem are identified. In steps 3 and 4, closing reconvergent gates (CRGs) and exit lines are computed. In step 2, the algorithm does not identify some SRGs which could be exit lines of the stem. As a result, the fault simulation may be incorrect for some faults. The commenters show this case using an example circuit. >