Dong-Shong Liang

Trivalued Memory Circuit Using Metal–Oxide–Semiconductor Field-Effect Transistor Bipolar-Junction-Transistor Negative-Differential-Resistance Circuits Fabricated by Standard SiGe Process

A trivalued memory circuit based on two cascoded metal–oxide–semiconductor field-effect transistor bipolar-junction-transistor negative-differential-resistance (MOS-BJT-NDR) devices is investigated. The MOS-BJT-NDR device is made of MOS and BJT devices, but it can show the NDR current–voltage characteristic by suitably arranging the MOS parameters. We demonstrate a trivalued memory circuit using the two-peak MOS-BJT-NDR circuit as the driver and a resistor as the load. The MOS-BJT-NDR devices and memory circuits are fabricated by the standard 0.35 µm SiGe process.

Novel voltage-controlled oscillator design by MOS-NDR devices and circuits

This paper describes the design of a voltage-controlled oscillator (VCO) based on the negative differential resistance (NDR) devices. The NDR devices used in the work is fully composed by the metal-oxide-semiconductor field-effect-transistor (MOS) devices. This MOS-NDR device can exhibit the NDR characteristic in its current-voltage curve by suitably arranging MOS parameters. The VCO is constructed by three low-power MOS-NDR inverter. This novel VCO has a range of operation frequency from 151MHz to 268MHz. It consumes 24.5mW in its central frequency of 260MHz using a 2 V power supply. This VCO is fabricated by 0.35 /spl mu/m CMOS process and occupied an area of 120 /spl times/ 86 /spl mu/m/sup 2/.

Four-valued memory circuit designed by multiple-peak MOS-NDR devices and circuits

This paper describes the design of a four-valued memory cell based on a three-peak MOS-NDR circuit. We connect three MOS-NDR devices in parallel that can create a three-peak current-voltage curve by suitably arranging the parameters. Due to its folding I-V characteristics, multiple-peak NDR device is a very promising device for multiple-valued logic application. This memory cell structure can be easily extended to implement more states in a memory circuit.

Logic circuit design based on MOS-NDR devices and circuits fabricated by CMOS process

We propose a new MOS-NDR device that is composed of the metal-oxide-semiconductor field-effect- transistor (MOS) devices. This device could exhibit the negative differential resistance (NDR) characteristics in the current-voltage characteristics by suitably modulating the MOS parameters. We design a logic circuit which can operate the inverter, NOR, and NAND gates. The devices and circuits are fabricated by the standard 0.35/spl mu/m CMOS process.

Investigation of MOS-NDR Voltage Controlled Ring Oscillator Fabricated by CMOS Process

A voltage-controlled ring oscillator (VCO) based on novel MOS-NDR circuit is described. This MOS-NDR circuit is made of metal-oxide-semiconductor emiconductor ield-effect-transistor ( MOS) devices that can exhibit the negative differential resistance (NDR) current-voltage characteristic by suitably arranging the MOS parameters. The VCO is constructed by three low-power ower MOS-NDR inverters. This novel VCO has a range of operation frequency from 38MHz to 162MHz. It consumes 24mW in its central frequency of 118MHz using a 2V power supply. This VCO is fabricated by 0.35μm CMOS process and occupy an area of 0.015 mm2.

New D-Type Flip-Flop Design Using Negative Differential Resistance Circuits

A novel D-type flip-flop designed using negative differential resistance (NDR) circuit based on standard 0.35 mum CMOS process is demonstrated. First we propose a new NDR circuit that is made of metal-oxide- semiconductor field-effect-transistor (MOS), but it can show the NDR characteristic in its current-voltage curve by suitably designing the MOS widths/lengths parameters. The flip-flop circuit is composed by two monostable and one monostable-bistable transition logic elements (MOBILE). The performance of these circuits is evaluated by using HSPICE.

A VHF Oscillator Design Based on BJT Active Load Differential Amplifier

In this paper, we present a VHF (Very High Frequency) band oscillator which mainly composed of a BJT active load differential amplifier (Diff. amp). We use H-spice to verify that the active load differential amplifier oscillator output frequency is 900 MHz at 2.0 volts power supply under CIC 0.18 um-Si process. We also use discrete devices on bread board to prove the circuit is an oscillator circuit. Those experiments show such an oscillator can work stably from 3.8 to 5.9 volts. Their output frequency will be 161.1 MHz, 186.7 MHz under 3.8 volts and 5.9 volts respectively. We use FFT (Fast Fourier Transform) diagram to analyse these oscillators and shows SNR (Signal-to-Noise Ratio) values. Finally, those experimental results reveal that the oscillator is a nice voltage controlled oscillator (VCO) and also have good SNR characteristics.

Five-State Logic Using MOS-HBT-NDR Circuit by Standard SiGe BiCMOS Process

The MOS-HBT-NDR device is made of metal-oxide-semiconductor field-effect-transistor (MOS) and heterojunction bipolar transistor (HBT) devices, but it can show the negative-differential-resistance (NDR) current-voltage characteristic by suitably arranging the MOS parameters. The authors demonstrate a five-valued logic circuit using the two-peak MOS-HBT-NDR circuit as the driver and another two-peak MOS-HBT-NDR circuit as the load. The design and simulation is based on the technique of the standard 0.35mum SiGe process

Frequency multiplier design using BiCMOS-based multiple-peak NDR circuit

We demonstrate a novel frequency multiplier using the negative differential resistance (NDR) circuit based on the standard 0.35 µm BiCMOS technique. This NDR circuit is made of standard Si-based metal-oxide-semiconductor field-effect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT). We can obtain the three-peak NDR current-voltage (I-V) characteristics by connecting three MOS-HBT-NDR circuits in parallel. These I-V characteristics show high peak-to-valley current ratios with 7.5, 16.8, and 12.1 for three peaks, respectively. Using the folded I-V characteristics, we design a frequency multiplier which can multiply the input saw-tooth signal by a factor of four. The fabrication of this NDR-based frequency multiplier is easier and more convenient compared to the traditional resonant tunneling structure which is implemented by the complicated molecular-beam-epitaxy (MBE) system.

Multiple-Valued Memory Design by Standard BiCMOS Technique

A novel multiple-valued memory circuit design using multiple-peak negative differential resistance (NDR) circuit based on standard SiGe process is demonstrated. The NDR circuit is designed based on the combination of metal-oxide-semiconductor field-effect-transistor (MOS) and hetero-junction-bipolar-transistor (HBT) devices. However, we can obtain the multiple-peak negative differential resistance curves by suitably designing the MOS widths/lengths parameters. The memory circuit use four-peak MOS-HBT-NDR circuit as the driver and four constant current sources as the load. When we control the current sources on and off alternatively, we can obtain a sequence of multiple-valued logic output.