Kwang-Jow Gan

Raman spectra of Si‐implanted GaSb

The variations of Raman spectra for Si‐implanted (100) GaSb with various doses and energies were investigated. Samples implanted at room temperature showed disorder or amorphous layer. In order to heal the damage layer, furnace annealing as well as rapid thermal annealing were used. We got a better structural recovery with increasing the annealing temperature or time, and rapid thermal annealing showed better results in comparison with conventional furnace annealing. The relative intensities of longitudinal optical phonons from Raman spectra by rapid thermal annealing samples were compared with those of unimplanted GaSb. It is found that a better recovery of damage layer is formed comparable to an unimplanted wafer when the annealing temperature is 600 °C for 30 s.

Low-Power Gate Driver Circuit for TFT-LCD Application

This paper presents a novel low-power gate driver circuit fabricated from glass by using hydrogenated amorphous silicon (a-Si:H) technology and a standard five-mask process. The tolerance of the threshold voltage shift of the proposed gate driver circuit can be estimated as 30 V by using an H-SPICE simulator. Measurement results indicate that the rising and falling times of the output waveform are equal to those in the initial state. Moreover, the proposed gate driver circuit can operate reliably at a high temperature (T = 120 °C) for over 360 h. Furthermore, the proposed gate driver circuit reduces power consumption by 77.3% over that of a conventional gate driver circuit.

Effects of trimethylantimonide/triethylgallium ratios on epilayer properties of gallium antimonide grown by low‐pressure metalorganic chemical vapor deposition

Undoped GaSb epitaxial layers were grown on (100) GaSb substrates by low‐pressure metalorganic chemical vapor deposition. The trimethylantimonide/triethylgallium mole fraction (V/III) ratios were varied at a growth temperature of 600 °C and growth pressure of 100 Torr. It was found that the layer morphologies were strongly dependent on V/III ratios. The mirrorlike surface can be easily obtained under the V/III ratio in the range of 6–8. The growth rate was about 1.75 μm/h. The epitaxial layers were characterized by photoluminescence(PL) measurements and electron diffraction patterns. The bound‐exciton peaks and strong acceptor band peak in the PL spectra were observed from the sample grown under a V/III ratio of 6.84. PL peak intensity was found to be a function of the V/III ratios. I‐V characteristics of the p‐n diodes fabricated on the sample of undoped GaSb/GaSb:Te was measured. The undoped acceptor carrier concentration and mobility were 9.47×1016 cm−3 (300 K), 1.60×1016 cm−3 (77 K), 275.3 cm2 /V s (300 K), and 491.6 cm2/V s (77 K), respectively.Undoped GaSb epitaxial layers were grown on (100) GaSb substrates by low‐pressure metalorganic chemical vapor deposition. The trimethylantimonide/triethylgallium mole fraction (V/III) ratios were varied at a growth temperature of 600 °C and growth pressure of 100 Torr. It was found that the layer morphologies were strongly dependent on V/III ratios. The mirrorlike surface can be easily obtained under the V/III ratio in the range of 6–8. The growth rate was about 1.75 μm/h. The epitaxial layers were characterized by photoluminescence(PL) measurements and electron diffraction patterns. The bound‐exciton peaks and strong acceptor band peak in the PL spectra were observed from the sample grown under a V/III ratio of 6.84. PL peak intensity was found to be a function of the V/III ratios. I‐V characteristics of the p‐n diodes fabricated on the sample of undoped GaSb/GaSb:Te was measured. The undoped acceptor carrier concentration and mobility were 9.47×1016 cm−3 (300 K), 1.60×1016 cm−3 (77 K), 275.3 cm2 /V s (3...

The Improvement of High-

The impact of the Si cap/SiGe layer on the Hf-based high-<i>k</i> /metal gate SiGe channel pMOSFET performance and reliability has been investigated. We proposed an optimized strain SiGe channel with a Si cap layer to overcome the Ge diffusion and confine the channel carriers in the strained SiGe layer without the formation of a significant parasitic channel at the interface. With this optimized Si/SiGe stack channel, a high-performance Hf-based high-<i>k</i>/metal gate SiGe pMOSFET can be obtained with an appropriate <i>V</i>_TH (~0.3 V), low <i>C</i> -<i>V</i> hysteresis ( <; 5 mV), and better I_ON - I_OFF , <i>V</i>_TH rolloff, and <i>V</i>_TH stability. By the way, the related interface trap density in the high-<i>k</i> gate stack layer can also be reduced, thus improving the devices NBTI and HCI stressing-induced reliability.

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Abstract Undoped GaSb epilayers have been grown on (100) GaAs semi-insulating substrates by low pressure metalorganic vapor phase epitaxy (MOVPE). The effects of growth temperatures and TMSb/TEGa mole fraction ratios on the epitaxial properties of surface morphology, growth rate, carrier concentration and hole mobility (measured at 300 and 77 K) have been studied. For TMSb/TEGa mole fraction ratio of 6.84, a smooth surface morphology can be obtained at growth temperature of 550°C. At 550°C, the epitaxial surface grown for V / III = 6.64 was more smooth and mirror-like than that grown for V / III = 6.84. The growth rate increases with growth temperature. The hole concentration increases and mobility decreases with growth temperature between 520 and 635°C for V / III = 6.84. For 550°C grown epilayers: as the V/III ratio increased above 6.64 or decreased below 6.64, the hole concentration increased and the hole mobility decreased. The lowest concentration 1.8 × 10 16 cm −3 (77 K ) and the highest mobility 1447 cm 2 /V s (77 K) can be obtained for a V/III ratio of 6.64 at 550°C.

/Metal Gate pMOSFET Performance and Reliability Using Optimized Si Cap/SiGe Channel Structure

A trivalued memory circuit based on two cascoded metal–oxide–semiconductor field-effect transistor bipolar-junction-transistor negative-differential-resistance (MOS-BJT-NDR) devices is investigated. The MOS-BJT-NDR device is made of MOS and BJT devices, but it can show the NDR current–voltage characteristic by suitably arranging the MOS parameters. We demonstrate a trivalued memory circuit using the two-peak MOS-BJT-NDR circuit as the driver and a resistor as the load. The MOS-BJT-NDR devices and memory circuits are fabricated by the standard 0.35 µm SiGe process.

Heteroepitaxial growth of gallium antimonide on GaAs by low pressure MOVPE

Three-peak current-voltage (I-V) characteristics can be obtained from the combination of two series-connected negative differential resistance (NDR) devices under certain conditions. We discuss these constraint conditions and demonstrate their role in the design of multipeak I-V characteristics based on NDR devices in series. These phenomena will provide some useful concepts in the multipeak circuit design. Especially, these novel multipeak I-V characteristics can be applied to the multiple-valued logic applications with less devices compared to the traditional structure that stacks N identical devices to obtain N peaks in the I-V curve.

Trivalued Memory Circuit Using Metal–Oxide–Semiconductor Field-Effect Transistor Bipolar-Junction-Transistor Negative-Differential-Resistance Circuits Fabricated by Standard SiGe Process

Abstract The three-peak current–voltage (I–V) characteristics can be obtained from the combination of two special series-connected resonant tunneling diodes (RTDs) under certain conditions. We will discuss and derive these constraint conditions in this paper. For lack of the RTD model in PSpice program, a large-signal model was proposed for simulating the I–V characteristics of the RTDs in PSpice. The simulated I–V characteristics are matched well with the measured and analyzed results. In applications, a four-valued memory circuit based on the three-peak I–V characteristics is demonstrated and simulated.

Novel multipeak current-voltage characteristics of series-connected negative differential resistance devices

Abstract The current-voltage ( I - V ) and extrinsic hysteresis phenomena in a series combination of two resonant tunneling diodes with identical and different electrical parameters are analyzed and simulated. The derived I - V characteristic of the series circuit can be applied to the design and estimation of multipeak I - V characteristic before the circuit accomplishment. Some equations are derived to facilitate the circuit design.

Simulation and analysis of negative differential resistance devices and circuits by load-line method and PSpice

This paper describes the design of a voltage-controlled oscillator (VCO) based on the negative differential resistance (NDR) devices. The NDR devices used in the work is fully composed by the metal-oxide-semiconductor field-effect-transistor (MOS) devices. This MOS-NDR device can exhibit the NDR characteristic in its current-voltage curve by suitably arranging MOS parameters. The VCO is constructed by three low-power MOS-NDR inverter. This novel VCO has a range of operation frequency from 151MHz to 268MHz. It consumes 24.5mW in its central frequency of 260MHz using a 2 V power supply. This VCO is fabricated by 0.35 /spl mu/m CMOS process and occupied an area of 120 /spl times/ 86 /spl mu/m/sup 2/.