Dong-Suk Shin

High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability

For the first time, we have successfully fabricated gate-all-around twin silicon nanowire transistor (TSNWFET) on bulk Si wafer using self-aligned damascene-gate process. With 10nm diameter nanowire, saturation currents through twin nanowires of 2.64 mA/mum, 1.11 mA/mum for n-channel TSNWFET and p-channel TSNWFET are obtained, respectively. No roll-off of threshold voltages, ~70 mV/dec. of substhreshold swing (SS), and ~20 mV/V of drain induced barrier lowering(DIBL) down to 30 nm gate length are observed for both n-ch and p-ch TSNWFETs

Negative bias temperature instability of carrier-transport enhanced pMOSFET with performance boosters

The effects of mobility boosters such as straining technologies and modified transport direction emerging for 65 nm pFET and beyond on negative bias temperature instability (NBTI) have been investigated. Although compressive silicon nitride film as contact etch stopper layer (CESL) increases the device performance of pFET, NBTI is degraded by excessive hydrogen from CESL depending on gate length and active width. In addition, induced mechanical strain in gate oxide plays an important role in NBTI degradation behavior. From NBTI on <100> p-channel transistor, it is found that NBTI is not influenced by channel direction and mobility change, but degraded by hydrogen incorporated CESL. Recessed SiGe source/drain (S/D) for high-performance pFET gives more resistant nature against NBTI degradation by elevated S/D structure even with compressive CESL containing high amount of hydrogen. The combination among performance booster for targeting device should be carefully balanced by considering performance gain and reliability

Sub-25nm single-metal gate CMOS multi-bridge-channel MOSFET (MBCFET) for high performance and low power application

Improving the MBCFET performance further, we have successfully fabricated single-metal-gate high-performance CMOS MBCFET with elevated flat source/drain (EF-S/D) formed by low temperature cyclic selective epitaxial growth (LTC-SEG) of Si. Due to the S/D engineering and LTC-SEG process, we could achieved the symmetric threshold voltage of 0.25V and -0.22V for TiN-gate n-channel MBCFET (nMBCFET) and p-channel MBCFET (pMBCFET), respectively. This single-metal MBCFET simultaneously satisfied the requirements of high-performance (HP) and low operating power (LOP) transistors in ITRS roadmap.

Dramatically enhanced performance of recessed SiGe source-drain PMOS by in-situ etch and regrowth technique (InSERT)

A novel mass-production-worthy in-situ etch and regrowth technique (InSERT) for recessed SiGe source-drain (SD) PMOS is introduced. The unique source drain extension (SDE) recess results in high drive current (ion) gains of 35 and 38% for shallow recess depths of 30 and 40nm, respectively, while keeping Vth and off leakage equal to those of control Si. InSERT provides three advantages that are higher ion, higher throughput, and no need for implant retuning when compared to the conventional ex-situ dry etch and regrowth technique which exhibits an ion current gain of 23%.

Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications

10nm logic technology using Si FinFET is developed for low power and high performance applications. Power-speed gain of 27% compared to 14nm technology node was obtained using four key developments: 1) advanced gate stack engineering enabling 4 multi-Vt devices, 2) 3rd generation Fin technology, 3) highly doped source/drain (S/D), and 4) contact resistance optimization. CVD liner for BEOL process was also applied for better metal fill capability. Finally yield of the smallest ever SRAM with 0.04um2 SRAM bit-cell size was demonstrated.

Development of thermal neutron SER-resilient high-k/metal gate technology

We report the experimental procedure and data that establishes the correlation between natural boron (B10) concentration and thermal neutron soft error rate (SER) in an advanced 28nm high-k/metal gate (HK/MG) technology node. Thermal neutron induced singe event upsets (SEU) depend on the concentration of B10 in the contact process adopted for boosting SRAM performance. However, as technology rapidly evolves in terms of transistor feature size and overall design complexity, B10 concentration needs to decrease so as to reduce thermal neutron SER risk. Optimization of contact and eSiGe process can provide a technology profile that is robust against thermal and high energy neutron SER.

Highly controllable cyclic selective epitaxial growth (CySEG) for 65nm CMOS technology and beyond

A new novel raised source/drain (RSD) process by using cyclic selective epitaxial growth (CySEG) has been firstly proposed to enhance device performance for 65nm CMOSFETs and beyond. CySEG is effective in reducing the gate poly depletion effect by elevating only the source/drain region without the growth on top of the poly gate. The CySEG process is effectively combined with disposable spacer integration in order to reduce the SEG thermal budget for CMOS scaling. The disposable spacer process with CySEG dramatically enhance the drive current by 23% for pFET and restore the degraded current performance for nFET. The current performance of nFET was further improved by the RSD structure with channel width decrease. The RSD effect on releasing the compressive stress induced by shallow trench isolation (STI) might describe the opposite current performance tendency of scaled nFET.

Chemically Homogeneous and Thermally Robust Ni1–xPtxSi Film Formed Under a Non-Equilibrium Melting/Quenching Condition

To synthesize a thermally robust Ni1-xPtxSi film suitable for ultrashallow junctions in advanced metal-oxide-semiconductor field-effect transistors, we used a continuous laser beam to carry out millisecond annealing (MSA) on a preformed Ni-rich silicide film at a local surface temperature above 1000 °C while heating the substrate to initiate a phase transition. The melting and quenching process by this unique high-temperature MSA process formed a Ni1-xPtxSi film with homogeneous Pt distribution across the entire film thickness. After additional substantial thermal treatment up to 800 °C, the noble Ni1-xPtxSi film maintained a low-resistive phase without agglomeration and even exhibited interface flattening with the underlying Si substrate.