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Dive into the research topics where Tetsuji Ueno is active.

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Featured researches published by Tetsuji Ueno.


international electron devices meeting | 2005

Negative bias temperature instability of carrier-transport enhanced pMOSFET with performance boosters

Hwa Sung Rhee; Ho Lee; Tetsuji Ueno; Dong-Suk Shin; Seung-Hwan Lee; Yihwan Kim; Arkadii V. Samoilov; Per-Ove Hansson; Min Kim; Hyong Soo Kim; Nae-In Lee

The effects of mobility boosters such as straining technologies and modified transport direction emerging for 65 nm pFET and beyond on negative bias temperature instability (NBTI) have been investigated. Although compressive silicon nitride film as contact etch stopper layer (CESL) increases the device performance of pFET, NBTI is degraded by excessive hydrogen from CESL depending on gate length and active width. In addition, induced mechanical strain in gate oxide plays an important role in NBTI degradation behavior. From NBTI on <100> p-channel transistor, it is found that NBTI is not influenced by channel direction and mobility change, but degraded by hydrogen incorporated CESL. Recessed SiGe source/drain (S/D) for high-performance pFET gives more resistant nature against NBTI degradation by elevated S/D structure even with compressive CESL containing high amount of hydrogen. The combination among performance booster for targeting device should be carefully balanced by considering performance gain and reliability


symposium on vlsi technology | 2005

Dramatically enhanced performance of recessed SiGe source-drain PMOS by in-situ etch and regrowth technique (InSERT)

Tetsuji Ueno; Hwa Sung Rhee; Seung-Hwan Lee; Ho Lee; Dong-Suk Shin; Yun-Seung Jin; Shigenobu Maeda; Nae-In Lee

A novel mass-production-worthy in-situ etch and regrowth technique (InSERT) for recessed SiGe source-drain (SD) PMOS is introduced. The unique source drain extension (SDE) recess results in high drive current (ion) gains of 35 and 38% for shallow recess depths of 30 and 40nm, respectively, while keeping Vth and off leakage equal to those of control Si. InSERT provides three advantages that are higher ion, higher throughput, and no need for implant retuning when compared to the conventional ex-situ dry etch and regrowth technique which exhibits an ion current gain of 23%.


symposium on vlsi technology | 2006

Improved 1/f Noise Characteristics in Locally Strained Si CMOS Using Hydrogen-Controlled Stress Liners and Embedded SiGe

Tetsuji Ueno; Hwa Sung Rhee; Ho Lee; Myung Sun Kim; Hans S. Cho; Hion Suck Baik; Youn Hwa Jung; Hyun-Woo Lee; Heung Sik Park; Cheol Lee; Geum-Jong Bae; Nae-In Lee

This paper reports the first experimental demonstration of improved 1/f noise characteristics in a locally strained Si MOS through hydrogen-controlled stress liners and embedded SiGe (eSiGe). For NMOS, the high hydrogen density (1times1022cm-3) in the stress liner results in three times more noise than that of PMOS. For PMOS, eSiGe proves to be superior to a compressive stress liner in noise due to the low hydrogen density in the system. The controlled stress does not generate interface states or other scattering centers, which increase noise, and only improves 1/f noise due to carrier mass reduction


international electron devices meeting | 2004

Highly controllable cyclic selective epitaxial growth (CySEG) for 65nm CMOS technology and beyond

Seung-Hwan Lee; Dong-Suk Shin; Hwa Sung Rhee; Tetsuji Ueno; Ho Lee Moon Han Park; Nae-In Lee; Ho-Kyu Kang; Kwang-Pyuk Suh

A new novel raised source/drain (RSD) process by using cyclic selective epitaxial growth (CySEG) has been firstly proposed to enhance device performance for 65nm CMOSFETs and beyond. CySEG is effective in reducing the gate poly depletion effect by elevating only the source/drain region without the growth on top of the poly gate. The CySEG process is effectively combined with disposable spacer integration in order to reduce the SEG thermal budget for CMOS scaling. The disposable spacer process with CySEG dramatically enhance the drive current by 23% for pFET and restore the degraded current performance for nFET. The current performance of nFET was further improved by the RSD structure with channel width decrease. The RSD effect on releasing the compressive stress induced by shallow trench isolation (STI) might describe the opposite current performance tendency of scaled nFET.


international workshop on junction technology | 2006

Self-Amorphizing Gas Cluster Ion Beam Technology and Combination with Laser Spike Anneal for Highly Scaled Source Drain Junction

Ho Lee; Hwa Sung Rhee; Tetsuji Ueno; Myung Sun Kim; Ji Hye Yi; Hye-jung Cho; Youngsu Chung; Seulgi Kim; Hion Suck Baik; L. Feng; Yun Wang; J. Hautala; W. Skinner; Geum-Jong Bae; Nae-In Lee; Ho-yu Kang

High energy borane (B2H6) gas cluster ion beam (GCIB) successfully enables a sub-10 nm box-shaped dopant profile without channeling tail, and steep gradient (2.5 nm/dec) in lateral direction. pFET using GCIB source/drain extension shows superior suppression of short channel effects and reduces the dependency of drive current on gate overlap capacitance variation for scaled devices. Moreover, the perimeter leakage component in p+/n-well junction was reduced compared to the conventional co-implantation process with pre-amorphization, which might come from novel self-amorphization mechanism by energized clusters without foreign impurities such as Ge and F. For further scaled devices, GCIB can provide more efficient boron activation by laser spike annealing (LSA) while maintaining the scaled extension profile by combination with the reduced temperature spike RTA


Archive | 2005

Transistor and method of manufacturing the same

Tetsuji Ueno; Hwa-Sung Rhee; Ho Lee; Dong-Suk Shin; Seung-Hwan Lee


Archive | 2005

Methods of fabricating a semiconductor device using a selective epitaxial growth technique

Dong-Suk Shin; Hwa-Sung Rhee; Tetsuji Ueno; Ho Lee; Seung-Hwan Lee


Archive | 2007

SEMICONDUCTOR DEVICE HAVING ANALOG TRANSISTOR WITH IMPROVED OPERATING AND FLICKER NOISE CHARACTERISTICS AND METHOD OF MAKING SAME

Tetsuji Ueno; Hwa-Sung Rhee; Ho Lee


Archive | 2006

Methods of forming NMOS/PMOS transistors with source/drains including strained materials and devices so formed

Ho Lee; Tetsuji Ueno; Hwa-Sung Rhe


Archive | 2007

Semiconductor device including field effect transistor and method of forming the same

Hwa-Sung Rhee; Tetsuji Ueno; Ho Lee; Myung-sun Kim; Ji-Hye Yi

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