Sung-young Lee

High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability

For the first time, we have successfully fabricated gate-all-around twin silicon nanowire transistor (TSNWFET) on bulk Si wafer using self-aligned damascene-gate process. With 10nm diameter nanowire, saturation currents through twin nanowires of 2.64 mA/mum, 1.11 mA/mum for n-channel TSNWFET and p-channel TSNWFET are obtained, respectively. No roll-off of threshold voltages, ~70 mV/dec. of substhreshold swing (SS), and ~20 mV/V of drain induced barrier lowering(DIBL) down to 30 nm gate length are observed for both n-ch and p-ch TSNWFETs

A novel multi-channel field effect transistor (McFET) on bulk Si for high performance sub-80nm application

We demonstrate highly manufacturable double FinFET on bulk Si wafer, named multi-channel field effect transistor (McFET) for the high performance 80nm 144M SRAM. Twin fins are formed for each transistor using our newly developed simple process scheme. McFET with L/sub G/=80nm shows several excellent transistor characteristics, such as /spl sim/5 times higher drive current than planar MOSFET, ideal subthreshold swing of 60mV/dec, drain induced barrier lowering (DIBL) of 15mV/V without pocket implantation, and negligible body bias dependency, maintaining the same source/drain resistance as planar transistor due to the unique feature of McFET.

High-Performance Twin Silicon Nanowire MOSFET (TSNWFET) on Bulk Si Wafer

Gate-all-around twin silicon nanowire MOSFET (TSNWFET) with 5-nm-radius channels on bulk Si wafer is successfully fabricated to achieve extremely high drive currents of 2.37 mA/mum for n-channel and 1.30 mA/mum for p-channel TSNWFETs with mid-gap TiN metal gate. It also shows good short channel effects immunity down to 30 nm gate length due to GAA structure and nanowire channel. The effect of bottom parasitic transistor in TSNWFET is also investigated.

A partially insulated field-effect transistor (PiFET) as a candidate for scaled transistors

Highly manufacturable partially insulated field-effect transistors (PiFETs) were fabricated by using Si-SiGe epitaxial growth and selective SiGe etch process. Owing to these technologies, pseudo-silicon-on-insulator (SOI) structures, partially insulating oxide (PiOX) under source/drain (PUSD) and PiOX under channel (PUC), could be easily realized with excellent structural and process advantages. We are demonstrating their preliminary characteristics and properties. Especially, in the PUSD PiFET, junction capacitance, leakage current, and DIBL in bulk devices could be reduced and the floating body problem in SOI devices was also cleared without any area penalty. Thus, this PiFET structure can be a promising candidate for the future DRAM cell transistor.

80 nm 512M DRAM with enhanced data retention time using partially-insulated cell array transistor (PiCAT)

An 80 nm 512M DDR DRAM with partially-insulated cell array transistor (PiCAT) was fabricated. Si/SiGe epitaxial growth and selective SiGe etch process were used to form PiOX (Partially-Insulating OXide) under source and drain of the cell transistor. Using these technologies, partial-SOI (Silicon-On-Insulator) structure could be realized with excellent structural and electrical advantages on bulk Si wafer. Self-limited shallow junction under source/drain and halo doping effect at the channel region were formed by PiOX. With PiCAT, junction leakage current and SCE (Short Channel Effect) were reduced, and excellent data retention time was obtained.

Life cycle assessment of tractors

This study was intended to evaluate the environmental impact, and potential improvements for a typical tractor model (LT360D) of LG Machinery Co., Ltd. The life cycle of this study includes all stages from raw material acquisition up to final disposal. The eco-indicator 95 method was employed to perform an impact assessment. The result of this study is expected to represent the environmental feature of typical diesel vehicles at each life cycle stage. This study is a starting point of building life cycle inventories for typical off-road diesel tractors. With this result, environmental weak points of the tractor have been defined, and major improvement strategies have been set up to develop the ‘Green Tractor’.

Damascene gate FinFET SONOS memory implemented on bulk silicon wafer

We successfully demonstrate highly scaled damascene gate FinFET SONOS memory implemented on bulk silicon wafer. The FinFET SONOS devices show extremely high program/erase speed, large threshold voltage shifts over 4V at 1/spl mu/s/12V for program and 50/spl mu/s/-12V for erase, good retention time, and acceptable endurance. Thus, in sub-50nm regimes, ultra high speed operation becomes possible by using FinFET SONOS structure without sacrificing retention time.

A novel multibridge-channel MOSFET (MBCFET): fabrication technologies and characteristics

We have demonstrated a novel three-dimensional multibridge-channel metal-oxide-semiconductor field-effect transistor (MBCFET). This transistor was successfully fabricated using a conventional complementary metal-oxide-semiconductor process. We introduce the fabrication technologies and electrical characteristics of MBCFET in comparison with a conventional planar MOSFET. The MBCFET has more benefits than a conventional MOSFET. It shows 4.6 times larger current drivability than a planar MOSFET. This is due to the vertically stacked multibridge channels. The subthreshold swing of MBCFET is 61 mV/dec, which is almost an ideal value due to the thin body surrounded by gate. Based on a simulation result, we show that the MBCFET will have a large on-off state current ratio at short channel transistors.

Sub 30 nm multi-bridge-channel MOSFET (MBCFET) with metal gate electrode for ultra high performance application

We have successfully fabricated sub 30nm N+ poly and TiN gate MBCFET (multi-bridge-channel field effect transistor) both on SOI wafers and bulk-Si wafers. Using TiN metal gate and 20nm multi bridge channels, we achieved the drive current of 2.3mA//spl mu/m that is the largest drive current ever reported for pMOSFETs with excellent subthreshold swing of 75mV/dec, and drain induce barrier lowering (DIBL) of 36mV/V. Large I/sub on//I/sub off/ ratio and excellent threshold voltage (V/sub t/) distribution were obtained using TiN metal gate to eliminate channel ion implantation minimizing the mobility degradation and dopant fluctuation.

Sub-25nm single-metal gate CMOS multi-bridge-channel MOSFET (MBCFET) for high performance and low power application

Improving the MBCFET performance further, we have successfully fabricated single-metal-gate high-performance CMOS MBCFET with elevated flat source/drain (EF-S/D) formed by low temperature cyclic selective epitaxial growth (LTC-SEG) of Si. Due to the S/D engineering and LTC-SEG process, we could achieved the symmetric threshold voltage of 0.25V and -0.22V for TiN-gate n-channel MBCFET (nMBCFET) and p-channel MBCFET (pMBCFET), respectively. This single-metal MBCFET simultaneously satisfied the requirements of high-performance (HP) and low operating power (LOP) transistors in ITRS roadmap.