Donghun Choi

InGaAs metal-oxide-semiconductor capacitors with HfO2 gate dielectric grown by atomic-layer deposition

The influence of various process conditions on the structural integrity and electrical properties of Al∕HfO2∕p-In0.13Ga0.87As metal-oxide-semiconductor capacitors was investigated. Room temperature capacitance voltage measurements revealed postdielectric deposition anneal reduced hysteresis by more than 0.5V and sulfur passivation of InGaAs improved the capacitance frequency dispersion properties as well as reduced interface trap density. At V=VFB−1V, the leakage current densities ∼1.3×10−7, 0.4×10−6, and 1.3×10−6A∕cm2 were measured in devices with annealed HfO2 (110 and 32A) and sulfur-passivated InGaAs (110A unannealed HfO2), respectively. Transmission electron microscopy revealed sharp epitaxial InGaAs/crystalline HfO2 and GaAs∕InGaAs interfaces.

Pre-atomic layer deposition surface cleaning and chemical passivation of (100) In0.2Ga0.8As and deposition of ultrathin Al2O3 gate insulators

We have developed and tested the efficacy of a method for pre-atomic layer deposition (ALD) surface preparation that removes native oxides from the (100) In0.2Ga0.8As surface and provides a clean starting surface for ALD of ultrathin Al2O3 layers. Successive wet etching by aqueous HCl and NH4(OH) solutions and in situ pre-ALD thermal desorption of residual elemental As were performed. Photoelectron spectra obtained after ALD of Al2O3 on In0.2Ga0.8As prepared by this method revealed that the interface was free of In, Ga, and As oxides. The resultant metal-oxide-semiconductor capacitors with Pt electrodes exhibited capacitance-derived equivalent oxide thicknesses as small as 1.8nm.

Free surfaces and multilayer interfaces in the GaAs/AlAs system

Semiempirical potential energy functions have been utilized for a variety of calculations in the Ga-Al-As system: (1) surface energies have been calculated for several orientations of GaAs; (2) ledge energies for the GaAs(001) (As terminated) surface show long range interaction effects with the ledge energy increasing with spacing; (3) GaAs(001)/AlAs(001) superlattices have been simulated for a range of interlayer spacings with the excess interfacial energy per interlayer increasing from 5 erg/cm2 at an interlayer spacing of 1 molecular layer (5.8 A) to 50 erg/cm2 at an interlayer spacing of 18 molecular layers (103.8 A).

Annealing condition optimization and electrical characterization of amorphous LaAlO3∕GaAs metal-oxide-semiconductor capacitors

The electrical properties of amorphous LaAlO3∕GaAs metal-oxide-semiconductor capacitors fabricated using molecular-beam deposition are investigated. The surface was protected during sample transfer between III-V and oxide molecular beam epitaxy chambers by a thick arsenic-capping layer. Amorphous LaAlO3 was deposited on c(4×4) and (2×4) reconstructed (100) GaAs surfaces. An annealing method, a low temperature-short time rapid thermal annealing (RTA) followed by a high temperature RTA, was developed, yielding extremely small hysteresis (∼30mV), frequency dispersion (∼60mV), and interfacial trap density (mid-1010eV−1cm−2).

Molecular-beam epitaxial growth of III–V semiconductors on Ge∕Si for metal-oxide-semiconductor device fabrication

We describe the fabrication of III–V metal-oxide-semiconductor (MOS) devices on Ge∕Si virtual substrates using molecular-beam epitaxy. Migration-enhanced epitaxy and low temperature normal GaAs growth produced a sufficiently smooth surface to deposit gate oxides. A 300nm thick GaAs buffer layer was grown, followed by a 10nm growth of In0.2Ga0.8As high mobility channel layer. An 8.5nm thick Al2O3 layer was deposited ex situ by atomic-layer deposition. Capacitance-voltage (C-V) characteristics show the unpinning of Fermi level. This work suggests this materials combination as a promising candidate for the design of advanced, nonclassical complementary MOS and optoelectronic devices on Si substrates.

Fermi-Level Depinning of GaAs for Ohmic Contacts

In summary, we successfully demonstrate the unpinning of the Fermi level in n-GaAs through the insertion of an ultrathin insulator to reduce the penetration of MIGS from the metal into the semiconductor. We are able to transform the current from rectifying Schottky behavior, to increased conduction, to tunneling limited, simply by increasing the SiN thickness, verifying the ability for SiN to modulate the barrier height. A minimum contact resistance and maximum reverse current is obtained for a SiN thickness of 1.5 nm. We expect this method can be used to make non-alloyed low resistance ohmic contacts to n-GaAs, and can be applied to unpin other III-V Fermi levels.

Surface Stress Tensor Mediation of the Ledge Nucleation/Growth Process with the Surface Reconstruction Process in GaAs

A new GaAs semiempirical potential energy function which utilizes both two-body and three-body contributions has been used to evaluate the surface energy and surface stress tensor for the (111) and (00 1 )(As-terminated) surfaces as well as for ledges on the (00 1 ) surface. Both surface and ledge reconstruction patterns appear to be driven by stress tensor considerations and a long range ledge-ledge interaction arises via the stress tensor. The impact of this finding on two dimensional cluster formation and nucleation at the growing surface is very substantial.

Fermi level depinning for the design of III–V FET source/drain contacts

High mobility III–V compounds is a strong contender for extending high performance logic beyond the 22 nm technology node [1–3]. However, demonstrations of exceptional III–V performance required device footprints on the µm-scale despite nm-scale gate lengths, in order to avoid source/drain shorting during contact alloying. The scaling of III–V FETs is severely limited by the unacceptably large lateral diffusion of the multilayer alloyed structures typically used for ohmic contacts [4]. In our recent work, we introduced a novel non-alloyed, highly scalable contact structure through the use of Al as a low workfunction metal on an unpinned Fermi level [5]. We use GaAs as a baseline III–V material, where the developed contact techniques can be extended to InGaAs and InSb, materials which are more technologically important [6]. In this work, we explain in detail the unpinning mechanisms and the rationale for the material selection. We demonstrate the same method can be applied to a variety of metals, Y, Er, Al, Ti, W, and Pt, providing much flexibility in the design of an ideal source/drain contact for III–V HEMTs/MOSFETs and Schottky Barrier FETs.

The Electrical Characterization of Molecular-Beam-Deposited LaAlO 3 on GaAs and its Annealing Effects

ABSTRACT The electrical properties of Al/LaAlO 3 /GaAs metal-oxide-semiconductor capacitors were investigated. A thick arsenic (As 2 ) capping layer was used to protect the GaAs surface from oxidation and contamination during the air exposure that occurred between the deposition of the GaAs and LaAlO 3 layers in different molecular-beam epitaxy systems. Amorphous LaAlO 3 was deposited on c(4×4) - and (2×4) - reconstructed (100) GaAs surfaces. Post dielectric deposition annealing was found to improve the capacitance-voltage ( C - V ) characteristics by eliminating frequency dispersion in the depletion and weak inversion regimes and diminished the bi-directional C-V hysteresis to 210 mV. Reasonably low gate leakage current was maintained after annealing. INTRODUCTION One of the approaches to realize low power and high-speed/frequency devices is using materials in which the carrier mobility is much higher than that of silicon, such as gallium arsenide (GaAs). For the past three decades, however, the lack of useful surface passivation for compound semiconductors has precluded development of metal-oxide-semiconductor (MOS) devices and caused high surface recombination parasitic in scaled devices. The oxidation and the metal deposition on III-V materials create a high interfacial trap density (