Dongpo Chen

Reconfigurable Dual-Channel Multiband RF Receiver for GPS/Galileo/BD-2 Systems

A fully integrated dual-channel multiband RF receiver is designed and implemented for next-generation global navigation satellite systems (GNSSs) in a 0.18-μm CMOS process. Its two reconfigurable signal channels can simultaneously process any two types of 2-, 4-, or 20-MHz bandwidth signals mainly located around the RF bands of 1.2 and 1.57 GHz for GPS, Galileo, and BD-2 (aka Compass) systems, while achieving better performance (die area, noise figure, gain dynamic range) than other state-of-the-art GNSS receivers. A digital automatic gain control loop consisting of a variable gain amplifier and nonuniform 4-bit ADC is utilized to improve the receivers robustness and performance in the presence of interferences. While drawing 25-mA current per channel from a 1.8-V supply, this RF receiver achieves a total noise figure of 2.5 dB/2.7 dB at 1.2/1.57 GHz, an image rejection of 28 dB, a maximum voltage gain of 110 dB, a gain dynamic range of 73 dB, and an input-referred 1-dB compression point of -58 dBm, with an active die area of 2.4 mm2 for single channel.

A Dual-Band GNSS RF Front End With a Pseudo-Differential LNA

This brief presents the design and the implementation of a dual-band radio-frequency (RF) front end for global navigation satellite system (GNSS) receivers. The dual-band RF front end is composed of a pseudo-differential low-noise amplifier (LNA), down-conversion mixers, and programmable gain amplifiers (PGAs), and can be configured to operate at 1.2 and 1.57 GHz, respectively. The pseudo-differential LNA incorporates an active single-ended-to-differential conversion using capacitive coupling compensation for an improved phase and amplitude imbalance. The high-linearity PGA has a tunable gain range of 18 dB with a 6-dB gain step and a 0.2-dB gain ripple across a 30-MHz band width. The proposed RF front end achieves a maximum voltage gain of 68/65 dB, a noise figure of 2.4/2.6 dB, and an input-referred 1-dB compression point of -42/-39 dBm at the 1.2-/1.57-GHz bands. The receiver draws 10 mA from a 1.8-V power supply. The RF front end is implemented in a 0.18-μm CMOS process, occupying a die area of 1.0 × 0.5 mm2.

Reconfigurable dual-channel tri-mode all-band RF receiver for next generation GNSS

A dual-channel fully integrated RF receiver is designed and implemented for next generation Global Navigation Satellite Systems (GNSS) in a 0.18μmCMOS process. Its two independent channels are capable of receiving 2MHz, 4MHz or 20MHz bandwidth signals around 1.2GHz and 1.57GHz, for GPS, Galileo, and Compass systems. Gain controls along with an all-digital automatic gain control (AGC) loop are implemented in each channel to improve the noise and anti-interference performance of the receiver. While drawing 25mA current per channel from a 1.8V supply, this receiver achieves a total noise figure of 2.5dB/2.7dB and a maximum voltage gain of 115dB/112dB at 1.2GHz/1.57GHz, respectively, with a die area of 2.4×3mm2 including ESD and I/O pads.

A compact automatic gain control loop for GNSS RF receiver

A compact automatic gain control (AGC) loop for GNSS RF receiver is presented in this paper. The proposed AGC loop circuit achieves higher integration and lower power by eliminating the bulky off-chip capacitor and charge pump circuit, which are widely used in traditional AGC. The proposed AGC consists of a programmable gain amplifier (PGA), a 2-bit flash analog to digital converter (ADC), and a novel AGC unit. The proposed AGC loop circuit is implemented in a 0.18µm CMOS process, and occupies a die area of 0.275mm2. Simulation results show that the proposed AGC loop has a 29.5dB control range and a settling time of less than 0.25 ms.

A dual-band LNA with active balun for GNSS receivers

This paper presents the design and implementation of a dual-band reconfigurable low noise amplifier (LNA) for multi-band GNSS receivers. The proposed LNA incorporates an active balanced-to-unbalanced (balun) conversion and a step gain control. The LNA also utilizes a constant gm biasing to maintain a constant LNA gain over process, voltage, temperature (PVT) variations. The operating frequency of the LNA can be configured at either 1.2GHz or 1.57GHz by off-chip matching network. The LNA is designed in a 0.18-µm CMOS process, occupying a die area of 0.65×0.55mm2, including ESD, power clamp and bonding pads. Post-simulation results show that the proposed dual-band LNA achieves a voltage gain of 25dB and 22dB, a noise figure (NF) of 2.1dB and 2.3dB, at 1.2GHz and 1.57GHz respectively. The LNA draws 3.5mA current from a 1.8V supply.

Low-power high-linearity area-efficient multi-mode GNSS RF receiver in 40nm CMOS

the integration of Global Navigation Satellite Systems (GNSS) receiver with other wireless functionalities, e.g., GSM, WCDMA, LTE, Bluetooth, and WiFi, brings up new design challenges due to constrained silicon area and power consumption, and especially the interferences from other wireless functionalities. A dual-channel multi-mode GNSS RF receiver, for reception of GPS-L1, GLONASS-B1, Compass-B1, and Galileo-E1, is proposed to address these challenges. A novel frequency plan and a reconfigurable complex band-pass filter enable the two multi-mode reception channels to share most circuit blocks and thus reduce the power consumption and silicon area. An N-path filter and adaptive gain control is implemented in the RF front-end to reject the out-of-band interferences for high linearity. Designed in a 40nm CMOS, the proposed multi-mode GNSS RF receiver, including the RF front-end, baseband filter and ADC, PLL, and VCO, achieves a total noise figure of 1.7dB, out-of-band (1710MHz) input 1dB compression point of −16.5dBm, while consuming a total power of 13.2mW.

AVCO with F-V linearization techniques for CNS application

An improved VCO for compass navigation system (CNS) application is presented. It has a linearized KVCO and is robust to varactor bias variations. A voltage limit circuit is proposed to ensure that the varactors work in the depletion region. To compensate for active loop filters lack of driving ability, a rail to rail opamp is used. Post-simulation results show that a better KVCO performance is achieved compared to the conventional one with tuning voltage changing from 0.15V to 1.65V. Implemented in a 0.18um CMOS process, the proposed VCO operates at 3.2 GHz with power supply of 1.8V.

Anti-interference pseudo-differential wideband LNA for DVB-S.2 RF tuners

A novel pseudo-differential wideband Low Noise Amplifier (LNA) for DVB-S.2 Radio Frequency (RF) tuners is proposed. Based on narrow-band source degenerated structure, the proposed wideband LNA, covering the Digital Video Broadcast-Satellite.2 (DVB-S.2) band, demonstrates a higher gain and a lower Noise Figure (NF) than traditional wideband LNAs. Furthermore, a pseudo-differential topology is proposed to separate and cancel the in-band interferences. Designed and simulated in a 0.18 um CMOS, the proposed wideband LNA demonstrates an NF better than 2.5 dB and an input matching better than -10 dB with a gain higher than 18 dB over the operating band from 950 MHz to 2150 MHz. The LNA also achieves a typical 30 dB suppression of the interferences from the GSM signals. The simulated input-referred 3rd-order intercept point (IIP3) is 9.45 dBm and the total current consumption is 12 mA from a 1.8 V power supply.

An auto-calibrating I/Q mismatch scheme for high image rejection GPS RF receiver

An auto-calibrating I/Q mismatch scheme for high image rejection Multi-mode Global Navigation Satellite Systems RF receiver is proposed in this paper. Due to gain and phase errors between I and Q paths, image rejection will be restricted at poor level from the mismatch instead of components themselves in the system. The proposed calibrating scheme included an analog image rejecter and a digital error detector corrects the mismatch to optimize the image rejection performance using bisection adaptive feedback concept. Within 0.5dB gain error and 3 degree phase error, the proposed auto-calibrating scheme followed by a 5th complex filter can achieve 53.5dB image rejection, compared with 28dB without the scheme. The whole circuit consumes 1.1mA at 1.8V.

Wideband dual-mode complementary metal–oxide–semiconductor receiver

A dual-mode complementary metal–oxide–semiconductor (CMOS) receiver operating from 1 to 2 GHz is presented. The proposed receiver employs a switchable low-noise amplifier (LNA) and two separated down-conversion paths to realise dual-mode operation. For receiving weak signals without large blockers, the receiver works in the high-gain mode which adopts the common gate (CG)–common source (CS) LNA and the active-mixer-based down-conversion path to achieve high gain and low noise figure (NF). In the case of large in-band blockers, the receiver works in the high linearity mode, which uses the LNA as a low-noise transimpedance amplifier followed by a 25% duty-cycle current-driving passive mixer and a transimpedance amplifier based on current buffer to obtain high in-band linearity. Implemented in a 0.18 μm CMOS technology, this receiver achieves 4.9 dB NF and a voltage gain range of 29.4–92.6 dB in high-gain mode, whereas +0.9 dBm in-band input-referred third-order interception and a voltage gain range of 15.8–20.1 dB in high linearity mode.