Tingting Mo

Reconfigurable Dual-Channel Multiband RF Receiver for GPS/Galileo/BD-2 Systems

A fully integrated dual-channel multiband RF receiver is designed and implemented for next-generation global navigation satellite systems (GNSSs) in a 0.18-μm CMOS process. Its two reconfigurable signal channels can simultaneously process any two types of 2-, 4-, or 20-MHz bandwidth signals mainly located around the RF bands of 1.2 and 1.57 GHz for GPS, Galileo, and BD-2 (aka Compass) systems, while achieving better performance (die area, noise figure, gain dynamic range) than other state-of-the-art GNSS receivers. A digital automatic gain control loop consisting of a variable gain amplifier and nonuniform 4-bit ADC is utilized to improve the receivers robustness and performance in the presence of interferences. While drawing 25-mA current per channel from a 1.8-V supply, this RF receiver achieves a total noise figure of 2.5 dB/2.7 dB at 1.2/1.57 GHz, an image rejection of 28 dB, a maximum voltage gain of 110 dB, a gain dynamic range of 73 dB, and an input-referred 1-dB compression point of -58 dBm, with an active die area of 2.4 mm2 for single channel.

Quantization Noise Suppression in Fractional-

A novel programmable frequency divider for quantization noise (QN) suppression in fractional-N phase-locked loops (PLLs) is presented in this paper. The proposed phase switching multi-modulus frequency divider (PS-MMFD) utilizes a novel glitch-free phase switching (PS) divide-by-0.5/1/1.5/2 cell to reduce the frequency division step to 0.5 and its QN induced by ΔΣ modulation is thus suppressed by additional 6 dB. Compared with other frequency dividers used for QN suppression, the proposed glitch-free PS-MMFD is more robust, can operate at higher input frequency and consumes less power. Detailed analysis and implementation of the proposed glitch-free PS-MMFD is demonstrated, followed by experimental results from a fully integrated ΔΣ fractional-N PLL utilizing the proposed QN suppression technique. Implemented in a 0.18 μm CMOS process, the proposed glitch-free PS-MMFD occupies an area of 0.38 mm × 0.25 mm and consumes 5 mA from a 1.8-V supply at an input frequency of 2 GHz. Measurement results also demonstrate the additional 6-dB QN suppression by the proposed technique.

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A 10bit 300MHz analog-to-digital converter is presented. It uses medium-resolution SAR ADC to replace low-resolution Flash ADC to solve the high power consumption problem. The structure of sharing the same residue amplifier in two channels can further reduce the power consumption and correct the gain error between different channels. The asynchronous clock generator for SAR comparator and the improved capacitor array structure help to decrease SAR ADCs decision time. Simulation results in 65nm shows that it could have ENOB of 9.1 bits at 300MHz sampling. And its power consumption is only about 15.4mW.

PLLs Utilizing Glitch-Free Phase Switching Multi-Modulus Frequency Divider

An auto-calibrating I/Q mismatch scheme for high image rejection Multi-mode Global Navigation Satellite Systems RF receiver is proposed in this paper. Due to gain and phase errors between I and Q paths, image rejection will be restricted at poor level from the mismatch instead of components themselves in the system. The proposed calibrating scheme included an analog image rejecter and a digital error detector corrects the mismatch to optimize the image rejection performance using bisection adaptive feedback concept. Within 0.5dB gain error and 3 degree phase error, the proposed auto-calibrating scheme followed by a 5th complex filter can achieve 53.5dB image rejection, compared with 28dB without the scheme. The whole circuit consumes 1.1mA at 1.8V.

A 300MHz 10b time-interleaved pipelined-SAR ADC

Proposed in this paper is a general parasitic-compatible LCR matching method suitable for

An auto-calibrating I/Q mismatch scheme for high image rejection GPS RF receiver

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Analysis of Input LCR Matched

-path filter. Analysis of a conventional

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-Path Filter

-type matching is extended to accommodate the case of the

A 4th-order N-path filter in 40nm CMOS with tunable Gm-C stage and reduced center-frequency offset

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