Peichen Jiang

Reconfigurable Dual-Channel Multiband RF Receiver for GPS/Galileo/BD-2 Systems

A fully integrated dual-channel multiband RF receiver is designed and implemented for next-generation global navigation satellite systems (GNSSs) in a 0.18-μm CMOS process. Its two reconfigurable signal channels can simultaneously process any two types of 2-, 4-, or 20-MHz bandwidth signals mainly located around the RF bands of 1.2 and 1.57 GHz for GPS, Galileo, and BD-2 (aka Compass) systems, while achieving better performance (die area, noise figure, gain dynamic range) than other state-of-the-art GNSS receivers. A digital automatic gain control loop consisting of a variable gain amplifier and nonuniform 4-bit ADC is utilized to improve the receivers robustness and performance in the presence of interferences. While drawing 25-mA current per channel from a 1.8-V supply, this RF receiver achieves a total noise figure of 2.5 dB/2.7 dB at 1.2/1.57 GHz, an image rejection of 28 dB, a maximum voltage gain of 110 dB, a gain dynamic range of 73 dB, and an input-referred 1-dB compression point of -58 dBm, with an active die area of 2.4 mm2 for single channel.

A Dual-Band GNSS RF Front End With a Pseudo-Differential LNA

This brief presents the design and the implementation of a dual-band radio-frequency (RF) front end for global navigation satellite system (GNSS) receivers. The dual-band RF front end is composed of a pseudo-differential low-noise amplifier (LNA), down-conversion mixers, and programmable gain amplifiers (PGAs), and can be configured to operate at 1.2 and 1.57 GHz, respectively. The pseudo-differential LNA incorporates an active single-ended-to-differential conversion using capacitive coupling compensation for an improved phase and amplitude imbalance. The high-linearity PGA has a tunable gain range of 18 dB with a 6-dB gain step and a 0.2-dB gain ripple across a 30-MHz band width. The proposed RF front end achieves a maximum voltage gain of 68/65 dB, a noise figure of 2.4/2.6 dB, and an input-referred 1-dB compression point of -42/-39 dBm at the 1.2-/1.57-GHz bands. The receiver draws 10 mA from a 1.8-V power supply. The RF front end is implemented in a 0.18-μm CMOS process, occupying a die area of 1.0 × 0.5 mm2.

Reconfigurable dual-channel tri-mode all-band RF receiver for next generation GNSS

A dual-channel fully integrated RF receiver is designed and implemented for next generation Global Navigation Satellite Systems (GNSS) in a 0.18μmCMOS process. Its two independent channels are capable of receiving 2MHz, 4MHz or 20MHz bandwidth signals around 1.2GHz and 1.57GHz, for GPS, Galileo, and Compass systems. Gain controls along with an all-digital automatic gain control (AGC) loop are implemented in each channel to improve the noise and anti-interference performance of the receiver. While drawing 25mA current per channel from a 1.8V supply, this receiver achieves a total noise figure of 2.5dB/2.7dB and a maximum voltage gain of 115dB/112dB at 1.2GHz/1.57GHz, respectively, with a die area of 2.4×3mm2 including ESD and I/O pads.

All-Digital Adaptive Module for Automatic Background IIP2 Calibration in CMOS Downconverters With Fast Convergence

An all-digital adaptive module for input-referred second-order intercept point (IIP2) calibration in CMOS downconverters is proposed. The proposed automatic background calibration scheme utilizes a modified least-mean-square algorithm with a variable update step to achieve fast convergence. An easily acquired and highly second-order-intermodulation-distortion-correlated reference input is used with delay estimation/optimization to improve the convergence efficiency and reduce the implementation complexity. The proposed all-digital adaptive module is implemented on a field-programmable gate array to calibrate the IIP2 of a 2.62-GHz downconverter fabricated in a 0.18-μm CMOS process. With the proposed automatic background IIP2 calibration, the measured IIP2 of the CMOS downconverter is improved by 21 dB from 62 to 83 dBm, while the IIP2 calibration converges in less than 0.1 ms with a 10-MHz clock, ten times faster than the conventional adaptive algorithm.

A dual-band LNA with active balun for GNSS receivers

This paper presents the design and implementation of a dual-band reconfigurable low noise amplifier (LNA) for multi-band GNSS receivers. The proposed LNA incorporates an active balanced-to-unbalanced (balun) conversion and a step gain control. The LNA also utilizes a constant gm biasing to maintain a constant LNA gain over process, voltage, temperature (PVT) variations. The operating frequency of the LNA can be configured at either 1.2GHz or 1.57GHz by off-chip matching network. The LNA is designed in a 0.18-µm CMOS process, occupying a die area of 0.65×0.55mm2, including ESD, power clamp and bonding pads. Post-simulation results show that the proposed dual-band LNA achieves a voltage gain of 25dB and 22dB, a noise figure (NF) of 2.1dB and 2.3dB, at 1.2GHz and 1.57GHz respectively. The LNA draws 3.5mA current from a 1.8V supply.

A low flicker noise and high IIP2 downconversion mixer for Zero-IF GSM receiver

This paper proposes the design of a low flicker noise and high input-referred IP2 (IIP2) down-conversion mixer for Zero-IF GSM receiver in 0.18um CMOS process. The current driven passive mixer topology is adopted due to its low flicker noise and high linearity instincts. Simulation results show that this mixer achieves a conversion gain of 23.1dB with 940MHz local oscillator input signal, a flicker noise corner frequency of 2.5KHz and out of band IIP2 above 70dBm at the total current of 17mA.

Adaptive calibration of IIP2 in direct down-conversion mixers with modified LMS algorithm

A new adaptive calibration scheme for IIP2 in direct down-conversion mixers is proposed for reduced implementation complexity and improved convergence time. The proposed IIP2 adaptive calibration scheme utilizes a modified least-mean-squares (LMS) algorithm with a variable update step and a highly IMD2-correlated reference input. Detailed implementation of the proposed IIP2 adaptive calibration is presented. Simulation results show that the proposed IIP2 adaptive calibration achieves a 40 dB suppression of mixers IMD2 and a 50 µs convergence time, which is 100 times faster than that of a conventional LMS adaptive algorithm.

Low noise low power two-stage modulator with injection locked LO divider in 65nm CMOS

This paper presents a two-stage modulator for low noise and low power design. The modulator is driven by LO and 2LO; by rejecting noise from the LO path, the modulator achieves a noise floor of −161dBc/Hz at an offset frequency of 40MHz. The modulator also enables the use of a low power injection locked frequency divider (ILFD) to generate quadrature LO. Supplied by 1.2V, the whole circuit consumes only 7.6mA. The modulator is designed in a 65nm CMOS process.

A low-noise WCDMA transmitter with 25%-duty-cycle LO generator in 65nm CMOS

This paper describes a 65nm CMOS low-noise WCDMA transmitter including direct quadrature voltage modulator and 25%-duty-cycle LO generator. In comparison with conventional approaches employing Gilbert mixers, the use of a passive voltage mixer, core of the transmitter, significantly improves the output noise and linearity performance. A divider directly generating 25%-duty-cyle LO is presented to drive the passive voltage mixer. Delivering 2dBm WCDMA output power at 2500 MHz, the transmitter achieves −44dBc ACLR at 5 MHz offset and −64dBc ACLR at 10 MHz offset, respectively. The noise floor at 2 dBm output is −163 dBc/Hz at the frequency offset above 40 MHz. The transmitter consumes a total power of 59 mW.

A 1.8V CMOS polar transmitter front-end for 900MHz EDGE system

A 900MHz low-noise high-linearity polar transmitter front-end for EDGE system is presented, including a multiplier as well as a driver amplifier. The whole circuit is implemented in IBM 0.18µm CMOS process. The multiplier and DA provide output power ranging from −30dBm to 4.5dBm, an ACPR of −63dBc at 400KHz offset and an output noise of −167dBm/Hz at 20MHz offset. The spurious around 2^nd and 3^rd harmonics are −46dBc and −39dBc respectively. The carrier suppression is −45dBc. The whole circuit consumes 23∼56mA from a 1.8V supply voltage according to different gain levels.