Dongwon Park

Design of CMOS Scholtz's monocycle pulse generator

In this paper, a new Scholtzs monocycle pulse generator is proposed and simulated on TSMC 0.18 /spl mu/m CMOS technology. Scholtzs monocycle pulse, which has more advantages than the others, is basically achieved from second derivative of Gaussian pulse. Gaussian pulse is roughly achieved on quadrant squarer circuit with hyperbolic tangent input, and then Scholtzs monocycle pulse is generated by second differential operations in passive components. It can be applied to pulse generator in UWB transmitter as well as the wavelet for a correlator in receiver.

Wide dynamic range and high SNR self-reset CMOS image sensor using a Schmitt trigger

A simple and robust self-reset image sensor design using Schmitt trigger circuit is presented. Offset and reset delay accumulations are compensated effectively so that a self-reset CMOS image sensor can exploit signal-to-noise ratio (SNR) improvement along with its wide dynamic range under multiple resets. It has been designed and simulated using 0.18 mum CMOS technology to show SNR improvement of 22.8 dB with 1000 self-resets. It also provides low power consumption and fewer components for pixel-level image sensor design.

A 105.6dB DR and 65dB peak SNR self-reset CMOS image sensor using a Schmitt trigger circuit

A self-reset pixel level CMOS image sensor (CIS) is designed and tested which provides simultaneous improvements in dynamic-range (DR) and SNR performances. The pixel is fabricated in 0.5-µm 3-metal 2-poly CMOS technology and resulted in DR of 105.6dB with 65dB of peak SNR improvements. A simple Schmitt trigger circuit with offset cancellation technique is utilized to achieve this performance which compensates for the reset offset, comparator offset and reset delay.

Analysis and Design of a Robust Floating Point CMOS Image Sensor

A robust floating point CMOS image sensor (CIS) is designed and tested. A detailed analysis for signal-to-noise ratio (SNR) of the floating point CIS including the effect of the exponent detection error is presented. Based on the analysis, a simple way to effectively remove the optimum integration time detection error is proposed. In addition, the proposed imager obtains the exponent at the beginning of the image capturing cycle, which provides a logarithmic image of the scene. A 32 times 24 prototype sensor including 4 transistors pixel array, 4 bit static random access memory (SRAM) array, 8 bit ADC and CDS block, and integration time control block was designed and fabricated using standard 0.5 mum CMOS process. It achieved 50.5 dB of dynamic range (DR) enhancement with 32 dB of peak SNR at 30 frames/s.

A simple and robust self-reset CMOS image sensor

A simple and robust self-reset pixel-level CMOS image sensor (CIS) has been designed and tested to verify the improvement of the signal-to-noise ratio (SNR) compare to the conventional asynchronous self-reset pixel-level CISs. It significantly reduces noise accumulation from multiple self-resets by replacing a comparator and redundant regenerative modules with a simple Schmitt trigger circuit.

40.4: Invited Paper: iDP Standard for an Internal Connection in a Large‐screen Display

This paper provides for a technical overview of iDP (Internal DisplayPort) Standard Ver. 1.0. The iDP is an open industry standard developed for transporting a video pixel stream from a TV/monitor controller SOC (system on chip) to a TV/monitor panel TCON within a TV/monitor chassis. This standard leverages the proven DisplayPort technology at its simplest form. Targeted at replacing LVDS, the iDP consists of Main Link and HPD signal, operating without sideband channel. Instead of AUX CH of DisplayPort Standard, the iDP uses HPD pulse to coordinate Link Training; an iDP sink device asserts an HPD pulse to prompt an iDP source device to transmit Link Training patterns over Main Link. Nominal iDP link rate of 3.24Gbps/lane enables the transport of FHD240Hz video stream with the pixel bit depth of 30 bits per pixel over 8 lanes (or differential pairs), as opposed to 48 differential pairs of Quad LVDS link. The permitted number of lanes per bank k 1 to 16 lanes inclusive, and the permitted number of banks k 1 or more, depending on a panel configuration. Using data throttling technique, an iDP source device enables an iDP sink device to regenerate the pixel clock synchronously from a link symbol clock as in f_pixel_clock = f_LinkSymbolClock * Mvid /48, where Mvid is an 8-bit integer value, thus allowing for further simplification of an iDP TCON implementation.

Synthesis of dispersive signals and applications in wireless communications

In this paper, we propose a novel synthesis algorithm for time-varying transformations of signals With dispersive structures or that have been transmitted in highly non-linear dispersive mediums. Our algorithms are based on transformation techniques that counteract the effects of non-linear dispersive group delay changes by converting them to constant or linear group delay changes. In particular, we apply the algorithm to synthesize a signal with hyperbolic group delay structure from its Altes Q-distribution (QD). Such algorithms are important in recovering relevant dispersive signal segments after processing such as filtering in the time-frequency plane. We demonstrate the importance of our new synthesis algorithms in suppressing dispersive time-varying interference or impulsive artifacts in dispersive mediums, such as the ocean, in wireless communications applications. We demonstrate that the new approach using synthesis of dispersive structures successfully improved the systems bit error rate performance when compared to the use of techniques that use synthesis of linear structures.