Doris Burckhart

HIPPI developments for CERN experiments

Attention is given to the High-Performance Parallel Interface (HIPPI), a new ANSI standard, using a minimal protocol and providing 100-Mbyte/s transfers over distances up to 25 m. Equipment using this standard is offered by a growing number of computer manufacturers. A commercially available HIPPI chipset allows low-cost implementations. A brief technical introduction to the HIPPI is given, followed by examples of planned applications in high-energy physics experiments, including the developments involving CERN: a detector emulator, a RISC, (reduced instruction set computer) processor based VMEconnection, a long-distance fiber-optics connection, and a HIPPI testbox.<<ETX>>

The CHI, a new Fastbus interface and processor

The CERN Host Interface (CHI) is a family of interfaces to interconnect Fastbus, VMEbus, and external host computers. The Fastbus interface consists of a processor board (CHI-P) and host-specific I/O ports allowing connection using fast parallel or serial interfaces. For efficiency in a data acquisition chain, the CHI-P contains a 1-MB triple-port memory which allows concurrent access by Fastbus (as master or slave), the host link, and the 4.5 MIPS onboard processor. The processor, an MC68030 with floating point coprocessor, also has 1 Mb of local memory and 1.25 Mb of EPROM (electrically programmable ROM). The hardware modularity allows the CHI-P to be used as an interface, general-purpose Fastbus test module, or an embedded Fastbus processor. The resident software supports its use in each of these modes. Remote procedure calls, an ISO-style transport service, and the Standard Routines for Fastbus are provided on the host and on the CHI-P, allowing the migration of software between the two. Menu-driven test software and an interactive interpreted/compiled language support its use in a test environment. >

The CERN Host Interface

The authors discuss the CERN Host Interface Project, which aims to provide modular interfaces between Digital Equipment Corporations VAX series computers and two popular high-energy physics buses, the VMEbus and FASTBUS. These user-programmable interfaces contain a powerful central processing unit, large data memories, and ports that allow the user to configure the interface for the required host computer and target bus. The software support and the optical data connection are described. >

Standard CAMAC Subroutines for on-Line Computers at CERN

The ESONE/IEEE/NIM standard CAMAC subroutines have been implemented on a variety of on-line computer systems at CERN. Computers range from 8-bit microprocessors to 32-bit minis (M6800, HP/1000, PDPl1, NORD, VAX) and CAMAC interfaces include dedicated crate controllers, branch drivers and system crate configurations. The subroutine package is now in widespread use at CERN, for example in large physics experiments where on-line systems comprise several types of computers and CAMAC interfaces. The implementation will be described with emphasis on areas in which extensions to the standard have been made.