Robert Andrew McLaren

S-LINK, a data link interface specification for the LHC era

In the Technical Proposals for the ATLAS, CMS and ALICE experiments at CERN, there is a requirement for several thousand data links. Although there is an obvious need for standardisation, this seems difficult to achieve as the links run at different speeds, over different distances and have various constraints of power consumption, size and radiation hardness. An additional complication is that today one cannot decide which will be the most cost effective technology for the implementation of the final links. Furthermore, one must allow designers of boards at each end of the link, for example read-out electronics and input buffers, to work in parallel with the development of the links. The S-LINK is a new concept which should provide the benefits of standardisation without these limitations. The S-LINK specification defines, at both ends of the link, a simple FIFO-like user interface which remains independent of the technology used to implement the physical link. The physical link provides transfer of event data and control words, error detection, optional flow control and test facilities. The paper describes the S-LINK specification and gives examples of the use of the S-LINK, the physical links being designed, and the test equipment that is being developed.

Results from an ATM-based event builder demonstrator

ATM switching fabrics are good candidates to implement high performance parallel event builders for the future data acquisition systems of the LHC experiments. We are studying their feasibility through simulations and implementation of event builder demonstrators. The impact of the event builder characteristic traffic pattern on the switch has been studied and methods to avoid congestion in the switch have been proposed. Event building algorithms and data acquisition protocols have been developed. Measurements made with a demonstrator and comparisons with simulation studies are presented. The scalability of the measurements is discussed.

HIPPI developments for CERN experiments

Attention is given to the High-Performance Parallel Interface (HIPPI), a new ANSI standard, using a minimal protocol and providing 100-Mbyte/s transfers over distances up to 25 m. Equipment using this standard is offered by a growing number of computer manufacturers. A commercially available HIPPI chipset allows low-cost implementations. A brief technical introduction to the HIPPI is given, followed by examples of planned applications in high-energy physics experiments, including the developments involving CERN: a detector emulator, a RISC, (reduced instruction set computer) processor based VMEconnection, a long-distance fiber-optics connection, and a HIPPI testbox.<<ETX>>

The CHI, a new Fastbus interface and processor

The CERN Host Interface (CHI) is a family of interfaces to interconnect Fastbus, VMEbus, and external host computers. The Fastbus interface consists of a processor board (CHI-P) and host-specific I/O ports allowing connection using fast parallel or serial interfaces. For efficiency in a data acquisition chain, the CHI-P contains a 1-MB triple-port memory which allows concurrent access by Fastbus (as master or slave), the host link, and the 4.5 MIPS onboard processor. The processor, an MC68030 with floating point coprocessor, also has 1 Mb of local memory and 1.25 Mb of EPROM (electrically programmable ROM). The hardware modularity allows the CHI-P to be used as an interface, general-purpose Fastbus test module, or an embedded Fastbus processor. The resident software supports its use in each of these modes. Remote procedure calls, an ISO-style transport service, and the Standard Routines for Fastbus are provided on the host and on the CHI-P, allowing the migration of software between the two. Menu-driven test software and an interactive interpreted/compiled language support its use in a test environment. >

The CERN Host Interface

The authors discuss the CERN Host Interface Project, which aims to provide modular interfaces between Digital Equipment Corporations VAX series computers and two popular high-energy physics buses, the VMEbus and FASTBUS. These user-programmable interfaces contain a powerful central processing unit, large data memories, and ports that allow the user to configure the interface for the required host computer and target bus. The software support and the optical data connection are described. >

Designing an S-LINK to PCI interface using an IP core

The S-LINK is a standard that defines the source and destination interfaces of a point-to-point data link. This standard is chosen for data transmission between front-end electronics and readout systems of some ongoing and future experiments at CERN, Geneva, Switzerland. This work presents the S32PCI64 interface that can move data from a 32-bit S-LINK Destination Card to any 32-bit or 64-bit PCI bus running at 33 MHz.

An overview of the Data Flow system for the NA48 experiment at CERN

The NA48 experiment at CERN is designed to measure the magnitude of direct CP-violation in the neutral kaon system. The experiment requires a Data Flow system which will run at up to 100 Mbytes/sec. Elements of the detector generate data which are presented to Optical Link Sources. Data arrive at the Data Merger which concatenates the various sub-events into a complete event. The data are then sent, via a HIPPI-link and a crossbar switch to one of several Alpha OSF/1 workstations for filtering, reconstruction and storage. Software applications control the Data Flow System include a Control Program which supervises the system, a Data Merger Controller Program which controls data merging and distribution and other tasks which supervise storage resources. This paper provides an overview of the hardware setup and the software tasks which control and monitor it. The current state of development of this system and results obtained during test beam running in June and September 1994 are presented.<<ETX>>

New buses and links for data acquisition

Abstract Bus standards for data acquisition have been vital for the construction and operation of medium and large HEP experiments. The recent industry bus standardisation effort will soon release the next generation of high performance buses and links for scalable systems. Prototype components, VLSI chips and board-level systems are already announced. Layers of the new bus specifications cover wide areas of applications and provide possibilities to define specific bus profiles by interest groups. New, innovative solutions which are needed for high rate experiments are becoming visible. These will provide novel architectural possibilities, very high bandwidth, fast silicon, industry support and new metric mechanical standards. Interconnected via standard bridges, different bus standards can be used to cover the varying requirements from the front ends to the computers.

Evolution of S-LINK to PCI interfaces

The S-LINK is a CERN developed standard that defines a point-to-point data link. In many applications and test systems the data transmitted over the link is moved to a PCI based computer. An overview of the evolution of S-LINK to PCI interfaces is given. The performance of these interfaces is presented and a description of the FILAR, a future PCI interface with four integrated inputs, is given.

A 10 Mbyte/s fibre optic link

This paper presents a fibre optic link (FOL) that has been developed for the NA48 experiment at CERN. About 15 FOLs will be used to transfer event data to the Data Merger (event builder) over a distance of 200 metres. The FOL has a very simple interface and is capable of transmitting data at a rate of over 10 Mbyte/s while performing error detection. The optical part of the FOL uses industry standard components. This, combined with its simplicity of use, makes the FOL suitable to be reused in a wide range of applications, which is shown by its use outside the NA48 experiment. >