H. Muller

SCI based data acquisition architectures

The scalable coherent interface (SCI) is an IEEE proposed standard (P1596) for interconnecting multiprocessor systems. The standard defines point-to-point connections between nodes, which can be processors, memories, or I/O devices. Networks containing a maximum of 64 K nodes with a bandwidth of 1 Gbyte/s between nodes can be constructed. SCI is an attractive candidate to serve as a backbone for high-speed, large-volume data acquisition systems such as those required by future experiments at the proposed Large Hadron Collider (LHC) at CERN. First results for a model of a large LHC experiment containing over 1000 nodes are reported. >

First experience with the scalable coherent interface

The research project RD24 is studying applications of the scalable coherent interface (IEEE-1596) standard for the Large Hadron Collider (LHC). First SCI node chips from Dolphin were used to demonstrate the use and functioning of SCIs packet protocols and to measure data rates. We present results from a first, two-node SCI ringlet at CERN, based on a R3000 RISC processor node and DMA node on a MC68040 processor bus. A diagnostic link analyzer monitors the SCI packet protocols up to full link bandwidth. In its second phase, RD24 will build a first implementation of a multi-ringlet SCI data merger. >

The CHI, a new Fastbus interface and processor

The CERN Host Interface (CHI) is a family of interfaces to interconnect Fastbus, VMEbus, and external host computers. The Fastbus interface consists of a processor board (CHI-P) and host-specific I/O ports allowing connection using fast parallel or serial interfaces. For efficiency in a data acquisition chain, the CHI-P contains a 1-MB triple-port memory which allows concurrent access by Fastbus (as master or slave), the host link, and the 4.5 MIPS onboard processor. The processor, an MC68030 with floating point coprocessor, also has 1 Mb of local memory and 1.25 Mb of EPROM (electrically programmable ROM). The hardware modularity allows the CHI-P to be used as an interface, general-purpose Fastbus test module, or an embedded Fastbus processor. The resident software supports its use in each of these modes. Remote procedure calls, an ISO-style transport service, and the Standard Routines for Fastbus are provided on the host and on the CHI-P, allowing the migration of software between the two. Menu-driven test software and an interactive interpreted/compiled language support its use in a test environment. >

The CERN Host Interface

The authors discuss the CERN Host Interface Project, which aims to provide modular interfaces between Digital Equipment Corporations VAX series computers and two popular high-energy physics buses, the VMEbus and FASTBUS. These user-programmable interfaces contain a powerful central processing unit, large data memories, and ports that allow the user to configure the interface for the required host computer and target bus. The software support and the optical data connection are described. >

New buses and links for data acquisition

Abstract Bus standards for data acquisition have been vital for the construction and operation of medium and large HEP experiments. The recent industry bus standardisation effort will soon release the next generation of high performance buses and links for scalable systems. Prototype components, VLSI chips and board-level systems are already announced. Layers of the new bus specifications cover wide areas of applications and provide possibilities to define specific bus profiles by interest groups. New, innovative solutions which are needed for high rate experiments are becoming visible. These will provide novel architectural possibilities, very high bandwidth, fast silicon, industry support and new metric mechanical standards. Interconnected via standard bridges, different bus standards can be used to cover the varying requirements from the front ends to the computers.

The evolution of the FASTBUS general purpose master (GPM)

The numerous programmable FASTBUS masters of the LEP data acquisition systems are mainly based on the Motorola 68-K microprocessor family. The GPM technique is used to couple the 68-K data bus to FASTBUS much like memory mapped I/O. A small set of addresses is provided to select all varieties of the FASTBUS protocol. The technique is called general purpose because any operation in FASTBUS can be written like a program. The discussion covers the architecture, applications software support, embedded processors, and hardware. >

submitter : Implementation of the VMM ASIC in the Scalable Readout System

The Scalable Readout System (SRS) developed by the RD51 collaboration is a versatile and multi-purpose approach, which is used with different front-end chips to transfer data from detectors to computers. Targeting mainly micropattern gaseous detectors, the system is also applicable for silicon strip or pad detectors. The most frequently used front-end chip today is the APV25, originally developed for the CMS pixel detector. In the scope of the ATLAS New Small Wheel upgrade, a new front-end chip, the VMM, is developed, which has significantly improved specifications compared to the APV25. We report on the implementation of the VMM in the Scalable Readout System carried out by the RD51 collaboration in the framework of a detector project related to the European Spallation Source ERIC. Due to the hierarchical design of the Scalable Readout System, only specific parts of the readout chain need to be adapted or designed, which is the carrier board for the front-end chip, an adapter card that connects to the common hardware of the system and the firmware for a field programmable gate array. In addition, we have developed dedicated software for slow control, data acquisition and online monitoring. The ∗Corresponding author Email address: michael.lupberger@cern.ch (M. Lupberger) Preprint submitted to Nuclear Instruments and Methods in Physics Research Section A, June 11, 2018 readout system has been tested in the laboratory and in particle beams and we present results which proof the functioning of the system, even though it is still in a prototype state.