Douglas A. Garrity

A Single Analog-to-Digital Converter That Converts Two Separate Channels (I and Q) in a Broadband Radio Receiver

An analog-to-digital converter (ADC) architecture that simultaneously converts two channels is presented. The ADC is intended for use in portable broadband radio receivers that employ in-phase (I) and quadrature (Q) signal paths and will provide an optimal combination of low cost, low power, and high performance. The architecture is pipeline based and employs two separate first stages followed by shared stages for the remainder of the pipeline. A clock generation system for generating all of the required nonoverlapping clock phases is also presented. A prototype ADC with 10 bit resolution and a 40 MHz sample rate that employs the proposed ADC architecture has been fabricated using a 90 nm all-digital CMOS process and occupies an area of 1.727 mm2 for a per-channel area of 0.864 mm2. The measured performance for the two-channel ADC is a peak signal-to-noise ratio (SNR) and signal-to-noise-plus-distortion ratio (SNDR) of 58.4 dB and 56.5 dB, respectively, and differential nonlinearity (DNL) and integral nonlinearity (INL) of -0.48/+0.58 LSB and plusmn1 LSB, respectively, with a power dissipation of 50 mW (including analog, digital, and clock generator power) from a 2.5 V supply (1.2 V for the digital section), giving a per-channel power dissipation of 25 mW.

Design Techniques to Improve Blocker Tolerance of Continuous-Time

Design techniques to provide robustness against loop saturation due to blockers in ΣA modulators are presented. Loop overload detection and correction are employed to improve the analog-to-digital converters (ADCs) tolerance to strong blockers; a fast overload detector activates the input attenuator, maintaining the ADC in linear operation. To further improve ADCs blocker tolerance, a minimally invasive integrated low-pass filter that reduces the most critical adjacent/alternate channel blockers is implemented. Measurement results show that the proposed ADC implemented in a 90nm CMOS process achieves 69dB dynamic range over a 20MHz bandwidth with a sampling frequency of 500 MHz and 17.1 mW of power consumption. The alternate channel blocker tolerance at the most critical frequency is as high as -5.5 dBFS while the conventional feedforward modulator becomes unstable at -23.5 dBFS of blocker power. The proposed blocker rejection techniques are minimally invasive and take less than 0.3 μs to settle after a strong agile blocker appears.

\Delta\Sigma

A CMOS chopper amplifier that achieves reduced input offset voltage and fast overload recovery time while maintaining bandwidths comparable to conventional operational amplifiers and requiring no external components is presented. The chopper amplifier consists of two folded cascode operational transconductance amplifiers (OTA) connected in a switched feed-forward configuration, and a third OTA that is used to realize a large capacitive load during normal operation, and a greatly reduced capacitive load during an overload condition. The circuit has been fabricated in a 2 mu m CMOS process. The measured input offset voltage is less than 50 mu V, the bandwidth is greater than 250 kHz, the maximum overload recovery time is less than 6.5 ms, and the DC gain is greater than 120 dB.<<ETX>>