Ira Miller

Analog design with Verilog-A

Verilog-A is a language to describe analog behavior. It is an extension to the IEEE 1364 Verilog Hardware Description Language (HDL) specification. A complete definition of the Verilog-A hardware description language, as proposed by the analog Technical Subcommittee of Open Verilog International (OVI), can be found in the Verilog-A Language Reference Manual (LRM). An LRM to describe mixed signal, Verilog-AMS, is in development and will be available in 1997. Several Verilog-A prototype simulators are now in development and three are available from commercial CAD tool providers. This paper contains information about Verilog-A, the motivation to develop it, some thoughts on model development, and an example of a Verilog-A module.

A new physical power MOSFET model for improved simulation in power electronic design

A physically based power MOSFET model is derived based on the charge-sheet analysis. This is the first time a charge-sheet approach has been successfully used in modeling a power MOSFET. The continuous nature of the charge-sheet model allows for the development of a continuous I-V model for the power MOSFET from subthreshold to saturation. The generalized form of the charge-sheet model enables the physical modeling of the nonuniform doping through the MOS channel region of the power MOSFET. A physical model of the power MOSFET drift region is combined with the channel model to give a complete physical system of equations which is solved numerically. The model includes detailed calculations of the drift region parameters including the variation of the internal depletion widths with external bias. The physical, continuous behavior of the model provides easy extraction of small signal parameters and interelectrode capacitances. Test measurements of real power MOSFETS are used as a comparison to support the model results.

A process and geometry driven device macro model for statistical simulation of bipolar ICs

A method of modeling bipolar semiconductor devices for circuit simulation is presented. Device layout geometric differences are accurately included in circuit simulation models without requiring a separate model for each layout geometry. To ensure that the simulated results closely match the measured performance, all parasitic junctions and capacitances are modeled in detail by utilizing subcircuit macros. Functional model parameters allow statistical circuit simulation from uncorrelated process parameters.<<ETX>>