Karan Kacker

Electrical/Mechanical Modeling, Reliability Assessment, and Fabrication of FlexConnects: A MEMS-Based Compliant Chip-to-Substrate Interconnect

Compliant free-standing structures can be used as chip-to-substrate interconnects. Such ldquocompliant interconnectsrdquo are a potential solution to the requirements that will be imposed on chip-to-substrate interconnects over the next decade. However, cost of implementation and electrical performance limit compliant interconnects. In our previous work, we have proposed a new compliant interconnect technology called FlexConnect to address these concerns with compliant interconnects. An innovative cost-effective MEMS-based fabrication process is used to fabricate these compliant interconnects. Sequential lithography and electroplating processes with up to two masking steps are utilized. Utilizing the proposed fabrication process, in this paper, FlexConnects are realized at a 100-mum pitch. High-frequency modeling of the electrical parasitics of the interconnect is performed. Through finite-element-based models, the advantage of using multiple electrical paths as part of the interconnect design is shown from a thermomechanical reliability perspective. Finally, taking advantage of the MEMS-based photolithographic fabrication process, a heterogeneous combination of FlexConnects and column interconnects is proposed. This approach is shown to be an additional avenue to attain improved electrical performance without compromising mechanical performance.

Accelerated thermal cycling: is it different for lead-free solder?

Accelerated test parameters such as extreme temperatures, temperature range, temperature ramps and dwell times have a major influence on deformation mechanisms in solder joints. With the increasing push for the introduction of lead-free solders, there is a need to revisit the accelerated thermal cycling regimes, as the solder composition can also influence the deformation mechanisms in solder joints. Time independent plastic deformation due to dislocations leading to slip bands and time dependent creep deformation due to diffusional flow of vacancies leading to grain boundary sliding are the two primary deformation mechanisms in solder joints. It is recognized, for example, that the lead-free solders creep 10 to 100 times slower than tin-lead solders under a given stress state. This paper examines the inelastic deformation mechanisms in lead and lead-free solders in BGA packages. Accelerated thermal cycling guidelines have been developed keeping in perspective the field-use conditions. The accelerated thermal cycles developed mimic the solder deformation mechanisms as in the field-use conditions and also reduce the time and the cost associated with accelerated testing. The finite-element models developed in this work are validated using experimental thermal cycling data and Moire interferometry data.

Low-K Dielectric Compatible Wafer-Level Compliant Chip-to-Substrate Interconnects

Performance, power, size, and cost requirements in the microelectronics industry are pushing for smaller feature size, innovative on-chip dielectric materials, higher number of interconnects at a reduced pitch, etc., without compromising the microelectronics reliability. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill material. These compliant interconnects are beneficial for integrated circuits (ICs) with low-K dielectric material. They are also potentially cost effective as they can be fabricated using conventional wafer fabrication infrastructure. In this paper we discuss the assembly and experimental reliability assessment, through thermal cycling, of G-Helix interconnects assembled on an organic substrate. Results from mechanical characterization experiments are also presented. It is shown that the proposed interconnects are not likely to delaminate or crack the low-K dielectric material. Also, a unique integrative approach is discussed, with interconnects having varying compliance for optimum electrical and mechanical performance.

Assembly and Reliability Assessment of Lithography-Based Wafer-Level Compliant Chip-to-Substrate Interconnects

Compliant chip-to-substrate “G-Helix” interconnects have been fabricated using electroplating and sequential lithography. Wafer-level, lead-free solder attachment, nounderfill processing, reworkability, large-area processing, scalability, and fine-pitch are some of the highlights of these interconnects. In this paper the assembly of such compliant interconnects on an organic substrate is presented. Results from mechanical compliance tests are also presented. The robustness of the compliant interconnects is also demonstrated through mechanical loading. An integrative system solution is presented where a combination of compliant interconnects and column interconnects is used to optimize the mechanical and electrical performance. Introduction Dramatic advances are taking place in the microelectronic industry. It is projected by the Semiconductor Industry Association [1] in their International Technology Roadmap for Semiconductors (ITRS) that in the next ten years, as the feature size in IC components shrinks to about 10 nm by 2015 [1], the chip-to-substrate or off-chip input-output interconnects would require to have a pitch of about 80 μm for area-array applications, and 15 μm for peripheral-array applications. A viable solution for such fine pitch interconnects must also be cost effective, reliable, and high performance. . Figure 1 : Schematic of a G-Helix Interconnect. The G-Helix interconnect is a lithography-based waferlevel electroplated compliant interconnect, that can be scaled to meet the fine-pitch chip-to-substrate interconnect requirements. A schematic representation of the G-Helix is provided in Figure 1. The proposed compliant interconnects have several advantages: 1) Force exerted by the interconnects on die bonding pads is minimal and will not crack or delaminate the low-K dielectric in the die, 2) The interconnects can accommodate the CTE mismatch between the die and the organic substrate as well as the non-planarity of the organic substrate, 3) The interconnects are reworkable and do not require underfill for thermo-mechanical reliability 4) The interconnects are wafer-level and are scalable with I/O pitch, 5) The interconnects utilize conventional wafer fab infrastructure for fabrication, and the fabrication processes is repeatable with good yield, 6) The interconnects can accommodate electrical, mechanical, and thermal requirements by a combination of helix and column interconnects, 7) Lead-free solder can be employed for the interconnect assembly to substrates, and therefore, the technology is environmentally friendly. The G-Helix interconnect consists of an arcuate beam and two end posts. The arcuate beam is incorporated into the design to accommodate the differential displacement in the planar directions (x and z). The two end posts connect the arcuate beam to the die and to the substrate. In our previous work [2, 3], we have discussed the characterization and optimization of the interconnect. The optimized G-Helix interconnect has a total standoff height of about 78 μm, a radius of 38 μm and a cross-section area of about 88μm. Based on finite-element simulations the optimized design has the following mechanical and electrical characteristics. Diagonal Mechanical Compliance: 9.068 mm/N Vertical Mechanical Compliance: 10.149 mm/N Max. Von-Mises Stress (Diagonal load): 175.55 MPa Max. Von-Mises Stress (Vertical load): 172.06 MPa Electrical Resistance: 43.63 mΩ Self Inductance: 0.08989 nH The fabrication of G-Helix interconnects is based on the lithography, electroplating and molding (LIGA-like) technologies, and can be integrated into wafer-level fine-pitch batch processing. Fabrication of a three-row 100μm pitch half-mirrored peripheral array of G-Helix interconnects on a 20 x 20mm silicon die has been described in [4] and is illustrated in Figure 2. In this paper we will discuss assembly of Helix interconnects on an organic substrate. Results from mechanical compliance experiments are also presented. A dieW H

A Heterogeneous Array of Off-Chip Interconnects for Optimum Mechanical and Electrical Performance

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 80 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnects are less likely to crack or delaminate the low-k dielectric material in current and future integrated circuits. The interconnects are potentially cost effective because they can be fabricated in batch at the wafer level and using conventional wafer fabrication infrastructure. In this paper, we present an integrative approach, which uses interconnects with varying compliance and thus varying electrical performance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermomechanical reliability concerns. The test vehicle design to assess the reliability and electrical performance of the interconnects is also presented. Preliminary fabrication results for the integrative approach are presented and show the viability of the fabrication procedure. The results from reliability experiments of helix interconnects assembled on an organic substrate are also presented. Initial results from the thermal cycling experiments are promising. Results from mechanical characterization experiments are also presented and show that the out-of-plane compliance exceeds target values recommended by industry experts. Finally, through finite element analysis simulations, it is demonstrated that the die stresses induced by the compliant interconnects are an order of magnitude lower than the die stresses in flip chip on board (FCOB) assemblies, and hence the compliant interconnects are not likely to crack or delaminate low-k dielectric material.

Design and Fabrication of FlexConnects: A Cost-Effective Implementation of Compliant Chip-to-Substrate Interconnects

Compliant free-standing structures can be used as chip-to-substrate interconnects. Such ldquocompliant interconnectsrdquo are a potential solution to the requirements that will be imposed on chip-to-substrate interconnects over the next decade. However, cost of implementation and electrical performance limit compliant interconnects. This paper presents two concepts to address this. First, an innovative, cost-effective fabrication process to realize compliant interconnects is proposed. Sequential lithography and electroplating processes with up to two masking steps are utilized. Such an approach potentially reduces the cost of fabricating compliant interconnects. Second, an innovative approach to designing compliant interconnects is proposed to improve electrical performance without compromising on mechanical reliability. The new approach uses parallel/multiple electrical paths as part of the compliant interconnect design. These concepts are integrated to realize a new compliant interconnect technology called FlexConnects. Utilizing the proposed fabrication process parallel-path FlexConnects are realized at a 100-mum pitch. Numerical simulations are used to demonstrate that the electrical performance of parallel-path FlexConnects (self inductance of ~ 37 pH) is enhanced without compromising on mechanical performance, validating the use of parallel/multiple electrical paths in the interconnect design.

Wafer-Level, Compliant, Off-Chip Interconnects for Next-Generation Low-K Dielectric/Cu IC’s

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors (ITRS) that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 70 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the CTE mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnect are less likely to crack or delaminate the low-K dielectric material in current and future ICs. The interconnects are also potentially cost effective as they can be fabricated using conventional wafer fabrication infrastructure. In this paper we present an integrative approach which uses interconnects with varying compliance and thus varying electrical preformance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermo-mechanical reliability concerns. We also discuss the reliability assessment results of helix interconnects assembled on an organic substrate. Results from mechanical characterization experiments are also presented.Copyright

Reliability Assessment and Failure Analysis of G-Helix, a Free-Standing Compliant Off-Chip Interconnect

Continued miniaturization in the microelectronics industry calls for chip-to-substrate off-chip interconnects that have 100 μm pitch or less for area-array format. Such fine-pitch interconnects will have a shorter standoff height and a smaller cross-section area, and thus could fail through thermo-mechanical fatigue prematurely. Also, as the industry transitions to porous low-K dielectric/Cu interconnect structures, it is important to ensure that the stresses induced by the off-chip interconnects and the package configuration do not crack or delaminate the low-K dielectric material. Compliant free-standing structures used as off-chip interconnects are a potential solution to address these reliability concerns. In our previous work we have proposed G-Helix interconnects, a lithography-based electroplated compliant off-chip interconnect that can be fabricated at the wafer level. In this paper we develop an assembly process for G-Helix interconnects at a 100 μm pitch, identifying the critical factors that im...