David L. Questad

Chip-Package-Interaction Modeling of Ultra Low-k/Copper Back End of Line

Ultra low-k (ULK, k=2.4) dielectric has weaker mechanical properties than first generation low-k films (k=3.0). The introduction of ULK into advanced back end of lines (BEOL) presents a significant challenge due to chip package interaction (CPI) where the packaged die is cycled over a temperature range and the resulting stress can cause ULK BEOL delamination. To avoid CPI failure detailed modeling from the package down to the BEOL must be coupled with quantitative material property measurement. In this paper multi-level finite element models have been used to investigate the parameters which drive CPI failure. It is found that the defect size in the BEOL and the package geometry are key drivers for delamination. Finally, this paper presents a detailed example of the utility of modeling to optimize dicing to reduce defect size, and provide targets for crackstop toughness, which has resulted in a successful reliability qualification of the porous SiCOH (k=2.4) for 45 nm BEOL technology with an organic flip-chip package.

Underfill selection strategy for Pb-free, low-K and fine pitch organic flip chip applications

The role of underfills is expanding from preserving solder joint reliability to also protecting fragile low-k chip dielectric layers. Traditionally, solder joints required stiff and rigid underfills. Today, low-k layers require more compliant underfill properties. Further complexity comes from the migration to Pb-free solders and changes in chip carrier materials. The myriad of candidates prohibits long term reliability testing of module hardware for every available underfill. A sequential three phase selection strategy is used to characterize and systematically eliminate undesirable candidates and to identify the few favorable underfills that have a high probability of successfully meeting module reliability requirements. The process includes use of industry practices as well as internally developed characterization methods. From an initial list of 20, the selection process identified five underfills for package qualification testing

Chip-to-package interaction for a 90 nm Cu / PECVD low-k technology

A summary of chip-to-package interaction (CPI) evaluations for a 90 nm PECVD low k technology will be discussed. This review will cover a 90 nm technology that uses Cu dual damascene interconnections with a SiCOH (K /spl sim/ 3.0) CVD BEOL insulator stack across multiple wirebond package types and flipchip C4 ceramic and organic packages. It will be shown that with the use of IBMs internally engineered SiCOH BEOL insulator, CPI is not an issue with this technology node.

Organic substrates for flip-chip design : A thermo-mechanical model that accounts for heterogeneity and anisotropy

Abstract We present a thermo-mechanical characterization of organic substrates that accounts for heterogeneity both in the in-plane and out-of-plane directions. Systematic observation of the board files of a number of substrates of commercial interest reveals primarily three recurrent topological arrangements of copper and polymer; for each arrangement, the in-plane effective thermo-elastic properties are calculated via appropriate composite materials models. The averaging process in the out-of-plane direction (i.e. the stacking effect) is performed using standard laminated plate theory. The model is successfully applied to various regions of three organic substrates of interest (mainly differing in core thickness): the analytically calculated effective Young’s moduli ( E ) and coefficients of thermal expansion (CTE) are shown to be typically within 10% of the experimental measurements. An important attribute of this model is its ability to provide substrate description at various levels of complexity: a few effective properties are outputted that can be useful for further purely analytical investigations; at the same time, the model provides the full stiffness matrix for each region of the substrate, to be used for more detailed finite elements simulations of higher-level structures (e.g. silicon die/underfill/substrate/cooling solution assemblies). Preliminary application of this model to the warp analysis of a flip-chip is presented in the end.

Chip Package Interaction for 65nm CMOS Technology with C4 Interconnections

This paper discusses the chip package interaction (CPI) for a 65 nm low k BEOL CMOS chip assembled to an organic package. Inter-level dielectrics with k~3.0 and k~2.7, with oxide terminations, were used in combination with both Sn/Pb and lead-free C4s. Various underfill compounds were tested to determine their effectiveness in mitigating chip stresses without significantly impairing C4 fatigue life. A summary of the reliability stress results will be presented.

Novel design and integration enhancements in the final polymeric passivation for improved mechanical performance and C4 electromigration in lead-free C4 products

Two key C4 reliability concerns for the current and next generation integrated circuits are electromigration (EM) and “white C4” bumps caused by the stresses induced by die-package interactions. This paper discusses novel design and integration changes in the final polymeric passivation via (FV) in order to mitigate white bump and chip-package interaction (CPI) stresses in the ultra-low k (ULK) BEOL levels and also meet lead-free C4 EM requirements. FV design changes such as strategically offsetting a single or multiple FV vias towards the center of the chip and thus to the compressive side of the C4 bump has been shown to reduce the stresses in the ULK levels due to chip package interactions and hence significantly reduce the number of white bump fails. Changing the shape of the FV via to strategically distribute current more uniformly through the C4 bumps has also been shown to improve the C4 EM performance significantly, while lowering the overall stresses in the chip. Effects of final passivation thickness and via diameter on the white bump stresses will also be discussed. Supporting white-bump, C4 EM and electrical/mechanical modeling data showing the benefits of the design and integration changes will also be discussed in detail in the paper.

Chip/Package Design and Technology Trade-offs in the 65nm Cell Broadband Engine

Technology migration of the Cell Broadband Enginetrade (BE) Microprocessor to 65 nm chip technology precipitated a redesign of the original IC packaging. While many of the design changes were necessitated by the chip technology migration, other modifications were implemented to enhance the robustness and overall manufacturability of the product. This paper will discuss key aspects of the 65nm chip technology that drove changes to the package design and also describe some of the modifications to enhance the manufacturability of the product. The paper will outline the statistical analysis, modeling, simulation and characterization employed in the electrical and thermal design, specification and tolerancing of the microprocessor package. The paper will be of specific interest to those involved in the cost-effective, high performance IC package design and development and will be of general interest to those developing and refining analysis methods employed in overall design and technology trade-offs in advanced packaging.

Thermal Development, Modeling and Characterization of the Cell Processor Module

Optimal package thermal design for todays high power processors is critical to meet demanding performance, cost, and reliability objectives. This paper describes the thermal characterization and development of the first generation CELL processor, developed jointly by Sony, Toshiba and IBM. The package not only provides the very high bandwidth necessary for electrical performance, but also achieves low thermal resistance to dissipate high power and maintain low die temperatures with superior reliability. The focus of the paper is the first level package. The target thermal resistance for the package is explained as determined from detailed 2nd level modeling and novel power map calculation and validation techniques are discussed. Thermal and mechanical modeling are used characterize the effects of the thermal interface material (TIM) on the thermal performance and mechanical response of the package. The thermal test strategy and the TIM characterization techniques are described. In summary, the paper describes the novel thermal modeling and characterization methodology used in the design process, allowing high heat flux in a low cost system application

Packaging the Cell Broadband Engine microprocessor for supercomputer applications

The Cell Broadband Enginetrade (Cell BE) processor initially designed for high-end consumer electronics, has been enhanced by IBM for supercomputer applications. The enhancements to the chip also necessitated the design and development of a new package. The modifications to the chip included replacement of the 3.2 Gb/s XDR interface with a 800 Mb/s DDR2 interface of equal bandwidth. This required the addition of several hundred chip-level connections (C4s) and package BGA balls. Incorporating this and other enhancements to the chip resulted in a ~20% larger chip and a larger and more complex package. Additional noise from this large memory interface also drove decoupling requirements that necessitated mounting capacitors on both the top and bottom sides of the package. This paper describes the design of this new package as well as the analysis and characterization techniques used to address the packaging concerns outlined above. It includes a comprehensive noise analysis as well as a thorough characterization of the DDR2 interface in the final prototypes. The paper also outlines the design and analysis of the power distribution to the various voltage domains on the chip. Along with electrical design and performance, the paper also includes finite element modeling of the mechanical stresses resident in this FCPBGA package. Finally, the concluding portions of the paper will discuss the trade-offs between electrical performance and mechanical stability, reliability and relative cost.

Role of FBEOL Al pads and hard dielectric for improved mechanical performance in lead-free C4 products

One of the major reliability concerns of current and next generation integrated circuits is mechanical failure due to stresses induced by the chip-package interactions (CPI). The packaged parts are subjected to thermal-mechanical stresses due to a mismatch of the coefficient of thermal expansion of the Si, lead-free C4 bumps, and the organic flip-chip substrate leading to mechanical delamination or cracking in the weaker low-k/ultra-low K films within the chip. This work discusses the role of Aluminum (Al) pads in the far-back-end-of-line (FBEOL) levels of the chip in CPI stress mitigation of the weak low-k and ultra-low k (ULK) BEOL levels. The affect of the Al pad thickness, size and shape on the CPI stresses have been studied by means of 3D mechanical finite element analysis. “White C4” bump data showing the benefits of increasing the thickness of the Al pads and growing the Al pad size to be larger than the under bump metallurgy (UBM) diameter in alleviating detrimental stresses from the weak BEOL levels is also been discussed in the paper. This paper also outlines through mechanical modeling and “white C4” bump data the reduction in CPI stresses in the weaker BEOL levels with increasing thickness of the FBEOL hard dielectric.