Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Douglas W. Kemerer is active.

Publication


Featured researches published by Douglas W. Kemerer.


custom integrated circuits conference | 1999

The first copper ASICs: A 12M-gate technology

Jeannie H. Panner; Thomas R. Bednar; Patrick H. Buffet; Douglas W. Kemerer; Douglas W. Stout; Paul S. Zuchowski

This paper describes the first CMOS ASIC logic family built with copper metallurgy. Chips with up to 12-million equivalent gates can be designed in the 0.16 /spl mu/m process. The technology, product characteristics, CAD system and first customer chips are discussed.


Archive | 2000

Method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox

Darren L. Anand; John E. Barth; John A. Fifield; Pamela S. Gillis; Peter Jakobsen; Douglas W. Kemerer; David E. Lackey; Steven F. Oakland; Michael R. Ouellette; William R. Tonti


Archive | 1996

Integrated circuit chip having gate array book personalisation using local interconnect

Douglas W. Kemerer; Douglas W. Stout


Archive | 1988

Method of combining gate array and standard cell circuits on a common semiconductor chip

Elliot L. Gould; Douglas W. Kemerer; Lance A Mcallister; Ronald A. Piro; Guy R Richardson; Deborah A Wellburn


Archive | 1995

Wiring design tool improvement for avoiding electromigration by determining optimal wire widths

David J. Hathaway; Douglas W. Kemerer; William J. Livingstone; Daniel Joseph Mainiero; Joseph Leonard Metz; Jeannie H. Panner


Archive | 2002

Support structures for wirebond regions of contact pads over low modulus materials

Lloyd G. Burrell; Douglas W. Kemerer; Henry A. Nye; Hans-Joachim Barth; E.F. Crabbe; David Wendell Anderson; Joseph Ying-Yuen Chan


Archive | 2008

Programmable on-chip sense line

Corey K. Barrows; Douglas W. Kemerer; Douglas W. Sinut; Peter A. Twombly


Archive | 2003

Integrated circuit chip having a ringed wiring layer interposed between a contact layer and a wiring grid

Thomas R. Bednar; Timothy W. Budell; Patrick H. Buffet; Alain Caron; James V. Crain; Douglas W. Kemerer; Donald S. Kent; Esmaeil Rahmati


Archive | 2008

Methods and circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications

Corey K. Barrows; Douglas W. Kemerer; Stephen G. Shuma; Douglas W. Stout; Oscar C. Strohacker; Mark S. Styduhar; Paul S. Zuchowski


Archive | 1997

Semiconductor wiring technique for reducing electromigration

David J. Hathaway; Douglas W. Kemerer; William J. Livingstone; Daniel Joseph Mainiero; Joseph Leonard Metz; Jeannie H. Panner

Researchain Logo
Decentralizing Knowledge