Dragan Bojic

mobilePDR : a mobile medical information system featuring update via Internet

This paper presents an analysis of usability of mobile prescription reference systems in medical practice, and presents implementation of mobilePDR (Physicians Desk Reference). Various aspects of mobilePDR are discussed: main functions, information content, performance and design issues, independent evaluation with other similar tools, and lessons learned from the system development.

Chapter One - A Systematic Approach to Generation of New Ideas for PhD Research in Computing

Abstract This article represents an effort to help PhD students in computer science and engineering to generate good original ideas for their PhD research. Our effort is motivated by the fact that most PhD programs nowadays include several courses, as well as the research component, that should result in journal publications and the PhD thesis, all in a timeframe of 3–6 years. In order to help PhD students in computing disciplines to get focused on generating ideas and finding appropriate subject for their PhD research, we have analyzed some state-of-the-art inventions in the area of computing, as well as the PhD thesis research of faculty members of our department, and came up with a proposal of 10 methods that could be implemented to derive new ideas, based on the existing body of knowledge in the research field. This systematic approach provides guidance for PhD students, in order to improve their efficiency and reduce the dropout rate, especially in the area of computing.

An Overview of Selected Heterogeneous and Reconfigurable Architectures

Abstract Node level heterogeneous architectures are gaining popularity because of their excellent performance exhibited in real world applications from various domains. The main advantages of these architectures are better price-performance and power–performance ratios compared to traditional symmetric CPU architectures. This article presents an overview of most interesting node level heterogeneous architectures, focusing on some common architectures, such as the NVIDIA and the ATI graphics processing units, the Cell Broadband Engine Architecture, the ClearSpeed processor, the field programmable gate array accelerator solutions from Maxeler MaxNodes, the SGI systems (RASC), and the Convey Hybrid-Core Computer. The presentation encompasses hardware resources and available software development tools for each of the mentioned architectures with both qualitative and quantitative comparisons. Toward the conclusion, the authors express their viewpoint on the future of heterogeneous computing.

An overview of selected hybrid and reconfigurable architectures

Node level heterogeneous architectures have become attractive during the last decade for several reasons: Compared to traditional symmetric CPUs, they offer high real-application performance and can be energy and/or cost efficient. In this paper, we give an overview of the state-of-the-art in heterogeneous computing, focusing on commonly found architectures: The Cell Broadband Engine Architecture (CBEA), NVidia graphics processing units (GPUs), and field programmable gate arrays (FPGAs) accelerators solutions from Maxeler MaxNodes (MAX) and SGI systems (RASC). We present a review of hardware, available software tools for each solution, a quantitative and a qualitative comparison of the architectures, and give our view on the future of heterogeneous computing.

Analysis of task effort estimation accuracy based on use case point size

The use case point (UCP) method is one of the most commonly used size estimation methods in software development. Applicability of UCP size for the project effort estimation is thoroughly investigated; however, little attention is devoted to the effort estimation of particular task types. The authors have created and cross-compared prediction models for estimating task-type efforts by means of UCP size using an Online analytical processing model and R packages on a set of 32 real-world projects, with the goal of facilitating analysis of the correlation between project sizes and effort required to complete task types. Requirements, scoping, functional specification, and functional testing task types have up to two times better estimation accuracies than project effort. Implementation has slightly better accuracy than the project effort, while the other task types are not correlated to the UCP size. Using estimates of the most correlated task types and other techniques, such as expert judgment for others, we improved the overall project effort prediction accuracy and decreased the error from 26 to 16%.

A Modified Hill-Climbing Algorithm for Knowledge Test Assembly Based on Classified Criteria

This paper presents our experience with the development of an automated knowledge test assembler. Items are selected from an item bank on the basis of precisely formulated formal criteria. The focus of our research was on the classification of criteria for item selection and on an algorithm that assembles a test using these criteria. The criteria are expressed through parameters of a heuristic function used to evaluate a test’s quality; they were derived from teaching experience and we consider them to be highly intuitive to teachers. Item selection is performed by searching a state space using modified hill-climbing. The proposed quality function is used to guide the search for the optimal test. The test assembler is implemented inside an in-house software system, developed for preparing and scoring of knowledge tests. We have shown a statistically significant improvement in the mean reliability of the tests assembled by our test assembler, compared to the tests assembled by a widely available state-of-the-art tool. The performance indicators of the test assembler were also measured and analyzed. The experiments’ results encourage both practical use of the assembler and further research.

Knowledge discovery potential in automated test assembly

Creating knowledge tests in academic institutions is a procedure that is frequently repeated, and which requires examiners effort and significant time invested. The procedure is complex and demands objectivity of the examiner, test consistency and reliability. Automating the procedure can improve objectivity and facilitate the process to the examiner. This paper analyses potential of the proposed method for automated test assembly based on existing test bank, using method knowledge discovery and the nearest neighbor algorithm.

Evaluation and classification of syntax information usage in determining short text semantic similarity

This paper outlines and categorizes ways of using syntax information in a number of algorithms for determining short text semantic similarity. Algorithm performance was evaluated using the results of a paraphrase detection test on the Microsoft Research Paraphrase Corpus. Among the described algorithms and approaches to using syntax information we identify those best suited for application in languages with limited electronic linguistic tools and, with that goal in mind, we propose a new algorithm classification.

Automated testing of L-IRL robot programming language parser

Parser testing represents the basis of compiler testing because the accuracy of parsing execution directly affects the accuracy of semantic analysis, optimization and object code generation. It should include tests for correct and expected, but also for unexpected and invalid cases. In this paper, techniques for testing the parser, as well as algorithms and tools for test sentence generation are discussed. Generation of negative test sentences by modifying the original language grammar is described. Positive and negative test cases generated by Grow algorithm and Purdom algorithm are applied to the testing of L-IRL robot programming language and obtained results are described in this paper.

A comparative evaluation of open source tools for multicore and reconfigurable computing

In this paper we evaluated several free and open source compiler tools in the domain of tightly coupled multicore and fine grain reconfigurable systems. We chose the classic x86, ibm cell, and FPGA accelerator boards as representatives of commodity hardware of today. Our point of view was that of a traditional programmer (vs. hardware developer), so we focused on parallelizing compilers, and computation models such as OpenMP, in order to evaluate not just performance, but also the ease of use and level of automation in exploiting parallelism. Our case studies are based on previous work of Gokhale et. al and are an extension of those in the context of technical advances. The major purpose of our work is to establish an infrastructure which enables us to do experiments that combine FPGA-oriented and multicore-oriented compilation for the maximal execution time improvement of a single scientific program.