Sasa Stojanovic

Chapter One - A Systematic Approach to Generation of New Ideas for PhD Research in Computing

Abstract This article represents an effort to help PhD students in computer science and engineering to generate good original ideas for their PhD research. Our effort is motivated by the fact that most PhD programs nowadays include several courses, as well as the research component, that should result in journal publications and the PhD thesis, all in a timeframe of 3–6 years. In order to help PhD students in computing disciplines to get focused on generating ideas and finding appropriate subject for their PhD research, we have analyzed some state-of-the-art inventions in the area of computing, as well as the PhD thesis research of faculty members of our department, and came up with a proposal of 10 methods that could be implemented to derive new ideas, based on the existing body of knowledge in the research field. This systematic approach provides guidance for PhD students, in order to improve their efficiency and reduce the dropout rate, especially in the area of computing.

Approach for estimating similarity between procedures in differently compiled binaries

Abstract Context Detection of an unauthorized use of a software library is a clone detection problem that in case of commercial products has additional complexity due to the fact that only binary code is available. Objective The goal of this paper is to propose an approach for estimating the level of similarity between the procedures originating from different binary codes. The assumption is that the clones in the binary codes come from the use of a common software library that may be compiled with different toolsets. Method The approach uses a set of software metrics adapted from the high level languages and it also extends the set with new metrics that take into account syntactical changes that are introduced by the usage of different toolsets and optimizations. Moreover, the approach compares metric values and introduces transformers and formulas that can use training data for production of measure of similarities between the two procedures in binary codes. The approach has been evaluated on programs from STAMP benchmark and BusyBox tool, compiled with different toolsets in different modes. Results The experiments with programs from STAMP benchmark show that detecting the same procedures recall can be up to 1.44 times higher using new metrics. Knowledge about the used compiling toolset can bring up to 2.28 times improvement in recall. The experiment with BusyBox tool shows 43% recall for 43% precision. Conclusion The most useful newly proposed metrics are those that consider the frequency of arithmetic instructions, the number and frequency of occurrences for instructions, and the number of occurrences for target addresses in calls. The best way to combine the results of comparing metrics is to use a geometric mean or when previous knowledge is available, to use an arithmetic mean with appropriate transformer.

An Overview of Selected Heterogeneous and Reconfigurable Architectures

Abstract Node level heterogeneous architectures are gaining popularity because of their excellent performance exhibited in real world applications from various domains. The main advantages of these architectures are better price-performance and power–performance ratios compared to traditional symmetric CPU architectures. This article presents an overview of most interesting node level heterogeneous architectures, focusing on some common architectures, such as the NVIDIA and the ATI graphics processing units, the Cell Broadband Engine Architecture, the ClearSpeed processor, the field programmable gate array accelerator solutions from Maxeler MaxNodes, the SGI systems (RASC), and the Convey Hybrid-Core Computer. The presentation encompasses hardware resources and available software development tools for each of the mentioned architectures with both qualitative and quantitative comparisons. Toward the conclusion, the authors express their viewpoint on the future of heterogeneous computing.

An overview of selected hybrid and reconfigurable architectures

Node level heterogeneous architectures have become attractive during the last decade for several reasons: Compared to traditional symmetric CPUs, they offer high real-application performance and can be energy and/or cost efficient. In this paper, we give an overview of the state-of-the-art in heterogeneous computing, focusing on commonly found architectures: The Cell Broadband Engine Architecture (CBEA), NVidia graphics processing units (GPUs), and field programmable gate arrays (FPGAs) accelerators solutions from Maxeler MaxNodes (MAX) and SGI systems (RASC). We present a review of hardware, available software tools for each solution, a quantitative and a qualitative comparison of the architectures, and give our view on the future of heterogeneous computing.

A Case Study of Hybrid Dataflow and Shared-Memory Programming Models: Dependency-Based Parallel Game Engine

Recently proposed hybrid dataflow and shared memory programming models combine these two underlying models in order to support a wider range of problems naturally. The effectiveness of such hybrid models for parallel implementations of dense and sparse algebra problems is well known. In this paper, we show another real world example for which hybrid dataflow models provide better support than traditional shared memory models. Specifically, we compare these models using the game engine parallelization as a case study. We show that hybrid dataflow models decrease the complexity of the parallel game engine implementation by eliminating or restructuring the explicit synchronization that is necessary in shared memory implementations. The corresponding implementations also exhibit good scala-bility and better speedup than the shared memory parallel implementations, especially in the case of a highly congested game world that contains a large number of game objects. Ultimately, on an eight core machine we were able to obtain 4.72x speedup compared to the sequential baseline, and to improve 49% over the lock-based parallel implementation based on work-sharing.

A survey of dual data cache systems

Dual data cache (DDC) systems have attracted considerable research effort in the past decade or so, with their Divide et Impera tactic. DDC systems divide data according to their access patterns and use different caching strategies on them. In the first part of this paper, one possible classification taxonomy, is proposed and described. The second part of this paper represents a survey of the existing solutions classified according to proposed criteria, presenting their organization, benefits, shortcomings, and intended use.

Comparison of Binary Procedures: A Set of Techniques for Evading Compiler Transformations

License violation analysis may require digital forensics in the performance of a time-consuming search in order to find out whether a binary code of a product contains a procedure that originates from a source code for which a license is required. The conducted experiment shows that the production of a binary code using an arbitrary compiler decreases results of the evaluated solutions up to 10 times. The best performing solution, among those evaluated, uses software metrics for assessing similarities between procedures and ranks procedures from the binary code according to their similarities with the target forensics procedure. This paper tries to improve the ranking by proposing five techniques for making similarities assessment more robust against compiler transformations. The proposed techniques filter stack instructions and transfer instructions, retain partial information about the instruction order, simulate inlining, and eliminate procedures that significantly differ from the searched procedure. The techniques are evaluated using a dataset based on the STAMP benchmark and re-evaluated using a dataset based on the BusyBox toolset. The evaluation shows that the use of the proposed techniques increases recall by 47 and 42% for the first and second datasets, respectively.

ERLE: Embedded run length image encoding

File format used for images in embedded devices is mostly determined by limited available resources and performances. This paper proposes a new file format named ERLE which is adapted for usage in embedded devices. The format is presented by explaining the benefits of using this file format on embedded devices and drawbacks of using the standard image formats for image processing on small footprint embedded devices. Moreover, ERLE file format sections are described, as well as compression algorithms that are used and main file auxiliary structures for faster random pixel access.

A comparative evaluation of open source tools for multicore and reconfigurable computing

In this paper we evaluated several free and open source compiler tools in the domain of tightly coupled multicore and fine grain reconfigurable systems. We chose the classic x86, ibm cell, and FPGA accelerator boards as representatives of commodity hardware of today. Our point of view was that of a traditional programmer (vs. hardware developer), so we focused on parallelizing compilers, and computation models such as OpenMP, in order to evaluate not just performance, but also the ease of use and level of automation in exploiting parallelism. Our case studies are based on previous work of Gokhale et. al and are an extension of those in the context of technical advances. The major purpose of our work is to establish an infrastructure which enables us to do experiments that combine FPGA-oriented and multicore-oriented compilation for the maximal execution time improvement of a single scientific program.