Duck-Jin Chung

Embedded face recognition based on fast genetic algorithm for intelligent digital photography

In this paper, we propose embedded face recognition (FR) to use in intelligent image system. For efficient FR VLSI design, we use a feature selection and feature extraction method based on Gabor wavelets using a fast genetic algorithm (FGA). Many FR systems are based on Gabor wavelet due to its desirable characteristics of spatial locality and orientation selectivity. However, the process of searching for features with Gabor wavelet is computationally expensive and has an unusual sensibility for variations such as illumination. To overcome these problems and use in real-time applications, we optimize Gabor wavelets parameters of translation, orientations and scales, which make it approximates a local image contour region by the use of hardware oriented FGA. From experimental results, we certify that our method shows recognition rate of over 97.27 % for FERET dataset, which exceeds the performance of the other popular methods

Design of a mixed prime factor FFT for portable digital radio mondiale receiver

To achieve better sound quality and to improve data reception, digital radio mondiale (DRM) offers a worldwide initiative to bring analog amplitude modulation (AM) radio into the digital era. DRM systems use coded orthogonal frequency division multiplexing (COFDM) modulation with a multilevel coding scheme to get high resistance to the multipath padding and interference. The bandwidth of a DRM passband signal is less than 20 kHz and the number of carriers used in orthogonal frequency division multiplexing (OFDM) modulation is relatively small. For this reason, DRM systems use non-power-of-two Fast Fourier Transforms (FFT) for OFDM demodulation, such processing gives way to more speed and power consumption in critical paths in DRM receivers. In this paper, we propose a mixed radix-2n and prime factor FFT algorithm for portable DRM receivers. Using the proposed architecture, we can reduce the processing time and energy consumption compared to conventional digital signal processor (DSP) based DRM receivers.

A Power Line Communication Modem Based on Adaptively Received Signal Detection for Networked Home Appliances

Power line communications provide a convenient and cost-effective solution for data transmission, because power mains are the most popular and widely distributed medium in the world. However, the time-variant and unpredictable channel environment for communication poses a major challenge. In this regard, we propose a robust power line modem based on adaptively signal detection techniques for networked home appliances. The modulation scheme used in this research is a chirped spread spectrum with a separate matched filter based on an adaptive threshold decision technique. In addition, we propose an adaptive retransmission technique based on flexible carrier frequency selection using a ram based look-up table (LUT) for improving carrier sense multiple access with collision avoidance (CSMA/CA) media access protocol. The proposed power line transceiver is realized in 0.35 mum CMOS technology and verified with networked various consumer electronic devices. The results show that the proposed power line communication modem is well qualified as a communication device for home automation .

Narrowband Physical Layer Design for WBAN System

This paper propose the design of PHY simulator for WBAN system in IEEE 802.15.6. Recently, WBAN system is most popular system in wireless communication. According to the technical requirement of the WBAN task group, many companies and research institutes have proposed physical layer architectures to provide fundamental technologies for the WBAN communication systems. Since there are various service scenarios for in-body or on-body applications, the physical layer proposals include UWB as well as narrowband techniques. The implemented WBAN PHY simulator (in this paper) is designed fixed point that is specified PPDU structure and modulation method in WBAN TG6. In the WBAN PHY case, the modulations method is changed by frequency band and data rate. After implementation of simulator, we are going to design WBAN for hardware implementation. We are supposed to implement architecture of a chip that has mixed mode, PSK and FSK in MICS baseband for WBAN. WBAN simulator is designed by using MATLAB.

Implementation of High Efficient CAVLC Encoder for H.264/AVC

This paper proposes the design and VLSI implement of high efficient Context-based Adaptive Variable Length Coding (CAVLC) encoder which adopted a modified Variable Length Coding (VLC) look up table technique and parallel processing. The proposed CAVLC encoder used upper and under buffer as input buffer to perform zigzag scanning with both way ordering. Because of this, the proposed CAVLC encoder can be read and write concurrently. Moreover, we design the CAVLC encoder procedure with parallel processing which uses two generators for information signals and control signals to operate CAVLC modules such as a coeff_token (TotalCeff and TrailingOnes) module, a level module, a total_zeros module, and a run_before module. The proposed CAVLC is prototyped in Verilog-HDL, implemented and synthesized with megnachip 0.18 µm CMOS tech. The synthesis result shows that the gate count is about 12K with the clock constraint of 140Mhz. The proposed CAVLC encoder is suitable for real-time video applications.

Time-synchronized Forwarding Protocol for Remote Control of Home Appliances Based on Wireless Sensor Network

This paper presents a time synchronized forwarding protocol for remotely controlling home appliances connected to wireless sensor networks (WSNs) that have extremely large latency for transferring data to another node. The protocol basically uses distributed time division multiple access (TDMA) and provides scalability by a self-organization function based on a virtual sensor line. Time synchronized forwarding and self organization protocols using virtual sensor lines achieve not only low latency but also low power consumption for future consumer applications .

A partially operated FFT/IFFT processor for low complexity OFDM modulation and demodulation of WiBro in-car entertainment system

Wireless broadband (WiBro) systems can provide high data rate wireless Internet access with personal subscriber station under the stationary or mobile environment. It is the orthogonal frequency division multiple access (OFDMA) in time division duplex (TDD) system with 768 useful subcarriers over a nominal bandwidth of 8.75 MHz at 2.3 GHz band and each frame is composed of 42 OFDM symbols, corresponding to 5 ms. For modulation and demodulation in the WiBro communication system, the fast Fourier transform (FFT) processing is the most speed and power consumption critical path. In this paper, we describe 4096 points FFT and inverse FFT processor for mobile in-car entertainment systems. To obtain low complexities, small computation power and distributed memory, partially operated over-sampling architecture is developed to meet the requirement of non-stopping and high-speed data throughput. From experiment results, we can show that our methods reduce the complexity about 37.8% and it is suitable to implementation in mobile devices for WiBro consumer application which is required small area and low-power such as multimedia data service.

A wireless sensor node processor with digital baseband based on adaptive threshold adjustment for emotional lighting system

In this paper, we present a wireless sensor node processor for emotional lighting system. Proposed wireless sensor node processor consists of an 8-bit embedded microcontroller, media access control (MAC) accelerator and digital baseband based on adaptive threshold adjustment (ATA) for enhancing the pseudo noise (PN) code acquisition. We fabricate a wireless sensor node processor using 0.18 mum CMOS technology and organize wireless sensor network for emotional lighting system. These results show it can be successfully applied in wireless sensor networks for further emotional consumer applications

An IEEE 802.11g WLAN digital baseband processor using hybrid channel estimation for wireless home A/V receivers

The delivery of digital multimedia data over wireless networks enables many useful consumer applications such as home entertainment. However, there are many performance-related issues associated with the delivery of time-sensitive multimedia content over current wireless communication systems such as those using the IEEE 802.11 standards. Among the most significant issues are the high error rates, because of the media characteristics, and signal attenuation with distance. In this paper, we present a robust digital baseband processor using hybrid channel estimation for wireless home audio-video receivers operating on an IEEE 802.11g wireless local area network (WLAN). The proposed hybrid channel estimation is a combined decision-directed and pilot-assisted method for perfect channel state information (CSI). Experimental results show that the proposed method increases system performance by about 3 dB over the least squares (LS) scheme at 100-ns root mean square (RMS) delay.

A SIMD neural network processor for image processing

Artificial Neural Networks (ANNs) and image processing requires massively parallel computation of simple operator accompanied by heavy memory access. Thus, this type of operators naturally maps onto Single Instruction Multiple Data (SIMD) stream parallel processing with distributed memory. This paper proposes a high performance neural network processor whose function can be changed by programming. The proposed processor is based on the SIMD architecture that is optimized for neural network and image processing. The proposed processor supports 24 instructions, and consists of 16 Processing Units (PUs) per chip. Each PU includes 24-bit 2K-word Local Memory (LM) and a Processing Element (PE). The proposed architecture allows multichip expansion that minimizes chip-to-chip communication bottleneck. The proposed processor is verified with FPGA implementation and the functionality is verified with character recognition application.