Kyu-Yeul Wang

Design of a mixed prime factor FFT for portable digital radio mondiale receiver

To achieve better sound quality and to improve data reception, digital radio mondiale (DRM) offers a worldwide initiative to bring analog amplitude modulation (AM) radio into the digital era. DRM systems use coded orthogonal frequency division multiplexing (COFDM) modulation with a multilevel coding scheme to get high resistance to the multipath padding and interference. The bandwidth of a DRM passband signal is less than 20 kHz and the number of carriers used in orthogonal frequency division multiplexing (OFDM) modulation is relatively small. For this reason, DRM systems use non-power-of-two Fast Fourier Transforms (FFT) for OFDM demodulation, such processing gives way to more speed and power consumption in critical paths in DRM receivers. In this paper, we propose a mixed radix-2n and prime factor FFT algorithm for portable DRM receivers. Using the proposed architecture, we can reduce the processing time and energy consumption compared to conventional digital signal processor (DSP) based DRM receivers.

A Power Line Communication Modem Based on Adaptively Received Signal Detection for Networked Home Appliances

Power line communications provide a convenient and cost-effective solution for data transmission, because power mains are the most popular and widely distributed medium in the world. However, the time-variant and unpredictable channel environment for communication poses a major challenge. In this regard, we propose a robust power line modem based on adaptively signal detection techniques for networked home appliances. The modulation scheme used in this research is a chirped spread spectrum with a separate matched filter based on an adaptive threshold decision technique. In addition, we propose an adaptive retransmission technique based on flexible carrier frequency selection using a ram based look-up table (LUT) for improving carrier sense multiple access with collision avoidance (CSMA/CA) media access protocol. The proposed power line transceiver is realized in 0.35 mum CMOS technology and verified with networked various consumer electronic devices. The results show that the proposed power line communication modem is well qualified as a communication device for home automation .

Narrowband Physical Layer Design for WBAN System

This paper propose the design of PHY simulator for WBAN system in IEEE 802.15.6. Recently, WBAN system is most popular system in wireless communication. According to the technical requirement of the WBAN task group, many companies and research institutes have proposed physical layer architectures to provide fundamental technologies for the WBAN communication systems. Since there are various service scenarios for in-body or on-body applications, the physical layer proposals include UWB as well as narrowband techniques. The implemented WBAN PHY simulator (in this paper) is designed fixed point that is specified PPDU structure and modulation method in WBAN TG6. In the WBAN PHY case, the modulations method is changed by frequency band and data rate. After implementation of simulator, we are going to design WBAN for hardware implementation. We are supposed to implement architecture of a chip that has mixed mode, PSK and FSK in MICS baseband for WBAN. WBAN simulator is designed by using MATLAB.

Implementation of High Efficient CAVLC Encoder for H.264/AVC

This paper proposes the design and VLSI implement of high efficient Context-based Adaptive Variable Length Coding (CAVLC) encoder which adopted a modified Variable Length Coding (VLC) look up table technique and parallel processing. The proposed CAVLC encoder used upper and under buffer as input buffer to perform zigzag scanning with both way ordering. Because of this, the proposed CAVLC encoder can be read and write concurrently. Moreover, we design the CAVLC encoder procedure with parallel processing which uses two generators for information signals and control signals to operate CAVLC modules such as a coeff_token (TotalCeff and TrailingOnes) module, a level module, a total_zeros module, and a run_before module. The proposed CAVLC is prototyped in Verilog-HDL, implemented and synthesized with megnachip 0.18 µm CMOS tech. The synthesis result shows that the gate count is about 12K with the clock constraint of 140Mhz. The proposed CAVLC encoder is suitable for real-time video applications.

Robust JPEG2000 Image Transmission over IEEE 802.15.4

There are so many needs for image transmission through the sensor network. To meet these needs, we propose AUEP(Adaptive Unequal Error Protection) scheme for JPEG2000 image transmission through the IEEE 802.15.4. The AUEP method assign adaptive code rate resulting from PER(Packet Error Rate). The results which are given through the experiments show that the decoding rate and image quality are improved by the proposed adaptive unequal error protection technique.

Low-latency implementation of DFT-based transform domain channel estimation system in Mobile WiMAX system

In this paper, low-latency implementation of adaptive discrete Fourier transform (DFT) based channel estimator for Mobile WiMAX system is proposed. DFT based channel estimation improve the performance by suppressing time domain noise. However, conventional method use fixed channel impulse response (CIR) length which can cause significantly performance degradation in fast fading channel. In order to overcome this disadvantage, we proposed low-latency threshold based adaptive CIR estimation scheme. The proposed architecture exploit fast Fourier transform characteristic to achieve low-latency implementation. Simulation results show that the proposed method outperforms the conventional DFT-based with low-latency implementation.

Prostate cancer classification processor using DNA computing technique

Recently, classification and gene selection of DNA microarray data are important in biomedical research. DNA microarray data provide useful information that can be used to discover the complex mechanism of cancer development. DNA computing techniques are alternative approaches to analyze the DNA microarray data.In this paper, we propose the VLSI implementation of a prostate cancer classification processor. The proposed architecture uses parallel and pipelined processing to improve speed and uses cyclic random masks to reduce memory size. We evaluated the prostate cancer classification processor by testing its performance on prostate cancer microarray data. From the experimental results, the proposed architecture reduced the memory size and classification time with little loss of classification accuracy.

Memory reduction methods for IEEE 802.16e mobile station

In this paper, we propose memory reduction methods for IEEE 802.16e mobile station. Proposed methods are modulation encoder and decoder for uplink allocation, FIFO sharing architecture in downlink synchronizer and replacing frame memory for received signal storing with memory for preamble and FIFO for burst data. Comparison results show that the proposed methods reduce the memory size about 74.5%, 32.2% and 85.2% compared with conventional methods, respectively.

CVD level prediction processor using DNA computing

We propose a CVD (Cardiovascular disease) level prediction processor which has reduced computational efforts and time with insignificant diminution of CVD diagnosis accuracy when compared to the conventional CVD level prediction methods. The proposed DNA computing algorithm for implementation of CVD level prediction processor uses masks for simple nonspecific hybridization. Using the proposed mask, we can reduce HW computational efforts. Besides this, we decrease processing time resulting by co-processing hybridizations with a number of parallel matching units. The proposed CVD level prediction processor diagnoses CVD data of patients within 3.4 us. Therefore, the proposed CVD level prediction processor can be applied in a CVD level diagnosis system.

Multi-input R23SDF-kR for efficient FFT processor in MIMO-OFDM systems

In this paper, we propose a multi-input R23SDF-kR architecture for efficient FFT processor in MIMO-OFDM systems with n-antennas at the transmitter and receiver. The proposed architecture is based on R23SDF for low complexity and it is operated to k times clock rate for multi-stream processing like MDC pipeline method in MIMO-OFDM systems. The proposed multi-input R23SDF-kR processor reduces the hardware complexity with similar or less computation in comparison of conventional MDC methods. Comparison results show that the proposed R23SDF-4R and R23SDF-8R reduce the area about 58% and 76% compared with the most area-efficient methods at 4 × 4 and 8 × 8MIMO channels, respectively.